linux-kernel - Re: [PATCH v5 02/12] x86/retpoline: Add initial retpoline support

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Date:   Sat, 6 Jan 2018 21:34:25 +0000
From:   Andrew Cooper <andrew.cooper3@...rix.com>
To:     Thomas Gleixner <tglx@...utronix.de>
CC:     David Woodhouse <dwmw@...zon.co.uk>,
        Andi Kleen <ak@...ux.intel.com>, Paul Turner <pjt@...gle.com>,
        LKML <linux-kernel@...r.kernel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Greg Kroah-Hartman <gregkh@...ux-foundation.org>,
        Tim Chen <tim.c.chen@...ux.intel.com>,
        Dave Hansen <dave.hansen@...el.com>,
        Kees Cook <keescook@...gle.com>,
        Rik van Riel <riel@...hat.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Andy Lutomirski <luto@...capital.net>,
        Jiri Kosina <jikos@...nel.org>, <gnomes@...rguk.ukuu.org.uk>,
        Thomas Lendacky <Thomas.Lendacky@....com>
Subject: Re: [PATCH v5 02/12] x86/retpoline: Add initial retpoline support

On 06/01/18 21:23, Thomas Gleixner wrote:
> On Sat, 6 Jan 2018, Andrew Cooper wrote:
>> On 06/01/18 11:49, David Woodhouse wrote:
>>> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
>>> index 372ba3f..40e6e54 100644
>>> --- a/arch/x86/kernel/cpu/common.c
>>> +++ b/arch/x86/kernel/cpu/common.c
>>> @@ -904,6 +904,11 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
>>>  
>>>  	setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
>>>  	setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
>>> +#ifdef CONFIG_RETPOLINE
>>> +	setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
>>> +	if (c->x86_vendor == X86_VENDOR_AMD)
>>> +		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
>> This isn't safe.  It needs to be dependant on finding that LFENCEs are
>> actually dispatch serialising.
>>
>> In particular, when virtualised, you'll most likely be saddled with the
>> hypervisors choice of setting, in which case you need to use retpoline
>> as a fallback.
> On bare metal we are sure, the virtualization part is a different question.

Leaving virtualisation to one side, how does this cope with pre-SSE2
hardware?

~Andrew