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Date: Sun, 21 Jan 2018 11:50:20 -0600 From: Tom Lendacky <thomas.lendacky@....com> To: David Woodhouse <dwmw@...zon.co.uk>, arjan@...ux.intel.com, tglx@...utronix.de, karahmed@...zon.de, x86@...nel.org, linux-kernel@...r.kernel.org, tim.c.chen@...ux.intel.com, bp@...en8.de, peterz@...radead.org, pbonzini@...hat.com, ak@...ux.intel.com, torvalds@...ux-foundation.org, gregkh@...ux-foundation.org Subject: Re: [PATCH v2 2/8] x86/cpufeatures: Add AMD feature bits for Prediction Command On 1/21/2018 3:49 AM, David Woodhouse wrote: > AMD doesn't implement the Speculation Control MSR that Intel does, but > the Prediction Control MSR does exist and is advertised by a separate > CPUID bit. Add support for that. > > Signed-off-by: David Woodhouse <dwmw@...zon.co.uk> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 2efb8d4..8c9e5c0 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -207,6 +207,7 @@ > #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ > #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ > > +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */ > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ > #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ > > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index df11f5d..4eb90b2 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, > { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, > { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, > + { X86_FEATURE_AMD_PRED_CMD, CPUID_EBX, 12, 0x80000008, 0 }, I replied to the previous version, but I'll add it here, too. This should be moved to the existing 0x80000008/EBX entry rather than have it in scattered. Also, there will be a total of three bits: IBPB: 0x80000008 EBX[12] IBRS: 0x80000008 EBX[14] STIBP: 0x80000008 EBX[15] Since IBRS and STIBP share the same MSR, if a processor only supports STIBP (MSR bit 1), for ease of software implementation the processor does not GP fault attempts to write bit 0. In a similar manner, if a processor only suppors IBRS (MSR bit 0), the processor does not GP fault attempts to write bit 1. Thanks, Tom > { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, > { 0, 0, 0, 0, 0 } > }; >
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