linux-kernel - Re: [PATCH v3 1/2] arm64: Branch predictor hardening for Cavium ThunderX2

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Date:   Mon, 22 Jan 2018 11:33:11 +0000
From:   Will Deacon <will.deacon@....com>
To:     Jayachandran C <jnair@...iumnetworks.com>
Cc:     Jon Masters <jcm@...masters.org>, marc.zyngier@....com,
        linux-arm-kernel@...ts.infradead.org, lorenzo.pieralisi@....com,
        ard.biesheuvel@...aro.org, catalin.marinas@....com,
        linux-kernel@...r.kernel.org, labbott@...hat.com,
        christoffer.dall@...aro.org
Subject: Re: [PATCH v3 1/2] arm64: Branch predictor hardening for Cavium
 ThunderX2

On Fri, Jan 19, 2018 at 04:22:47AM -0800, Jayachandran C wrote:
> Use PSCI based mitigation for speculative execution attacks targeting
> the branch predictor. We use the same mechanism as the one used for
> Cortex-A CPUs, we expect the PSCI version call to have a side effect
> of clearing the BTBs.
> 
> Signed-off-by: Jayachandran C <jnair@...iumnetworks.com>
> ---
>  arch/arm64/kernel/cpu_errata.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 70e5f18..45ff9a2 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -338,6 +338,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
>  		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
>  		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
>  	},
> +	{
> +		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
> +		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
> +		.enable = enable_psci_bp_hardening,
> +	},
> +	{
> +		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
> +		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
> +		.enable = enable_psci_bp_hardening,
> +	},
>  #endif

Thanks.

Acked-by: Will Deacon <will.deacon@....com>

Will