linux-kernel - Re: [PATCH] clk: meson: add axg misc bit to the mpll driver

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Date:   Tue, 30 Jan 2018 20:12:55 +0100
From:   Jerome Brunet <jbrunet@...libre.com>
To:     Neil Armstrong <narmstrong@...libre.com>
Cc:     Stephen Boyd <sboyd@...eaurora.org>,
        Michael Turquette <mturquette@...libre.com>,
        Kevin Hilman <khilman@...libre.com>,
        linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: meson: add axg misc bit to the mpll driver

On Fri, 2018-01-19 at 16:42 +0100, Jerome Brunet wrote:
> On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
> change (expect for mpll2 strangely). Looking at the vendor kernel, it
> turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
> is required.
> 
> Setting this bit solves the problem and the mpll rates are back to normal
> 
> Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
> Signed-off-by: Jerome Brunet <jbrunet@...libre.com>

Applied to clk-meson next/drivers