linux-kernel - Re: [PATCH v6 21/41] ARM: da850: add new clock init using common clock framework

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 2 Feb 2018 12:05:08 -0600
From:   David Lechner <david@...hnology.com>
To:     Sekhar Nori <nsekhar@...com>, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Cc:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Kevin Hilman <khilman@...nel.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Adam Ford <aford173@...il.com>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 21/41] ARM: da850: add new clock init using common
 clock framework

On 02/02/2018 08:20 AM, Sekhar Nori wrote:
> On Saturday 20 January 2018 10:44 PM, David Lechner wrote:
>>   void __init da850_init_time(void)
>>   {
>> +#ifdef CONFIG_COMMON_CLK
>> +	void __iomem *pll0, *pll1, *psc0, *psc1;
>> +	struct regmap *cfgchip;
>> +	struct clk *clk;
>> +	struct clk_hw *parent;
>> +
>> +	pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
>> +	pll1 = ioremap(DA850_PLL1_BASE, SZ_4K);
>> +	psc0 = ioremap(DA8XX_PSC0_BASE, SZ_4K);
>> +	psc1 = ioremap(DA8XX_PSC1_BASE, SZ_4K);
>> +
>> +	cfgchip = da8xx_register_cfgchip();
>> +	if (WARN(IS_ERR(cfgchip), "failed to register CFGCHIP syscon"))
>> +		return;
>> +
>> +	clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
>> +
>> +	da850_pll_clk_init(pll0, pll1);
>> +
>> +	da8xx_cfgchip_register_div4p5(cfgchip);
>> +
>> +	da8xx_cfgchip_register_async1(cfgchip);
>> +
>> +	clk = clk_register_fixed_factor(NULL, "async2", "pll0_auxclk", 0, 1, 1);
>> +	clk_register_clkdev(clk, NULL, "i2c_davinci.1");
>> +	clk_register_clkdev(clk, "timer0", NULL);
>> +	clk_register_clkdev(clk, NULL, "davinci-wdt");
> 
> I think its better to get these clkdevs registered in
> da850_pll_clk_init() itself.

Sounds good to me.

> 
>> +
>> +	clk = da8xx_cfgchip_register_async3(cfgchip);
>> +
>> +	/* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */
>> +	parent = clk_hw_get_parent_by_index(__clk_get_hw(clk), 1);
>> +	if (parent)
>> +		clk_set_parent(clk, parent->clk);
>> +	else
>> +		pr_warn("%s: Failed to find async3 parent clock\n", __func__);
>> +
>> +	da850_psc_clk_init(psc0, psc1);
>> +
>> +	clk = clk_register_fixed_factor(NULL, "rmii", "pll0_sysclk7", 0, 1, 1);
>> +	clk_register_clkdev(clk, "rmii", NULL);
> 
> Like in da830, can drop this rmii clock, I think.
> 
> Thanks,
> Sekhar
>