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Date:   Tue, 13 Feb 2018 20:40:09 +0300
From:   "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
To:     Ingo Molnar <mingo@...hat.com>, x86@...nel.org,
        Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <hpa@...or.com>
Cc:     Andrei Vagin <avagin@...tuozzo.com>, linux-kernel@...r.kernel.org,
        "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
Subject: [PATCH] x86/boot/compressed/64: Do not truncate gdt address

Before going to 32-bit trampoline we need to load GDT to make sure that
we have the table with 32-bit code segment.

The load was implemented incorrectly and the table address is truncated
to 32-bit. It causes problems if gdt is above 4G.

Reported-and-tested-by: Andrei Vagin <avagin@...tuozzo.com>
Fixes: b4b56015ed1c ("x86/boot/compressed/64: Handle 5-level paging boot if kernel is above 4G")
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@...ux.intel.com>
---
 arch/x86/boot/compressed/head_64.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 70b30f2bc9e0..99a0e7993252 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -332,7 +332,7 @@ ENTRY(startup_64)
 
 	/* Make sure we have GDT with 32-bit code segment */
 	leaq	gdt(%rip), %rax
-	movl	%eax, gdt64+2(%rip)
+	movq	%rax, gdt64+2(%rip)
 	lgdt	gdt64(%rip)
 
 	/*
-- 
2.15.1

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