lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Sun, 25 Feb 2018 14:19:51 +0200 From: Andy Shevchenko <andy.shevchenko@...il.com> To: Baolin Wang <baolin.wang@...aro.org> Cc: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, devicetree <devicetree@...r.kernel.org>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>, Mark Brown <broonie@...nel.org> Subject: Re: [PATCH v2 3/3] gpio: Add Spreadtrum PMIC EIC driver support On Sat, Feb 24, 2018 at 12:44 PM, Baolin Wang <baolin.wang@...aro.org> wrote: > The Spreadtrum PMIC EIC controller contains only one bank of debounce EIC, > and this bank contains 16 EICs. Each EIC can only be used as input mode, > as well as supporting the debounce and the capability to trigger interrupts > when detecting input signals. > +/* > + * These registers are modified under the irq bus lock and cached to avoid > + * unnecessary writes in bus_sync_unlock. > + */ > +enum { REG_IEV, REG_IE, REG_TRIG, CACHE_NR_REGS }; One item per line. > +static int sprd_pmic_eic_direction_input(struct gpio_chip *chip, > + unsigned int offset) > +{ > + /* EICs are always input, nothing need to do here. */ > + return 0; > +} > + > +static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset, > + int value) > +{ > + /* EICs are always input, nothing need to do here. */ > +} Remove both. Look at what GPIO core does. > + value |= debounce / 1000; Possible overflow. > + for (n = 0; n < chip->ngpio; n++) { > + if (!(BIT(n) & val)) for_each_set_bit(). At some point you may need just to go across lib/ in the kernel and see what we have there. -- With Best Regards, Andy Shevchenko
Powered by blists - more mailing lists