linux-kernel - Re: [PATCH 1/6] ARM: dts: stm32: Add sdio pins definition for stm32f7

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 1 Mar 2018 10:17:39 +0000
From:   Patrice CHOTARD <patrice.chotard@...com>
To:     Alexandre TORGUE <alexandre.torgue@...com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "lee.jones@...aro.org" <lee.jones@...aro.org>
CC:     "mcoquelin.stm32@...il.com" <mcoquelin.stm32@...il.com>
Subject: Re: [PATCH 1/6] ARM: dts: stm32: Add sdio pins definition for stm32f7

Hi Alex

On 03/01/2018 10:51 AM, Alexandre Torgue wrote:
> Hi Patrice
> 
> On 03/01/2018 10:43 AM, patrice.chotard@...com wrote:
>> From: Patrice Chotard <patrice.chotard@...com>
>>
>> Add sdio pins definition for the 2 sdio instances embeds in stm32f746.
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard@...com>
>> ---
>>   arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 62 
>> ++++++++++++++++++++++++++++++++++
>>   1 file changed, 62 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi 
>> b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
>> index f518de184e52..fb40f0835dd4 100644
>> --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
>> +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
>> @@ -222,6 +222,68 @@
>>                       slew-rate = <2>;
>>                   };
>>               };
>> +
>> +            sdio_pins: sdio_pins@0 {
>> +                pins {
>> +                    pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 
>> D0 */
>> +                         <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
>> +                         <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
>> +                         <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
>> +                         <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
>> +                         <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
>> +                    drive-push-pull;
>> +                    slew-rate = <2>;
>> +                };
>> +            };
> 
> if you have 2 pins groups, please use '_a' for the first one. You could 
> have something like:
> 
> sdio_pins_a
> sdio_od_pins_a
> 
> and
> 
> sdio_pins_b
> sdio_od_pins_b

Ok, i prepare a v2

Thanks

Patrice

> 
>> +            sdio_pins_od: sdio_pins_od@0 {
>> +                pins1 {
>> +                    pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 
>> D0 */
>> +                         <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
>> +                         <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
>> +                         <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
>> +                         <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
>> +                    drive-push-pull;
>> +                    slew-rate = <2>;
>> +                };
>> +
>> +                pins2 {
>> +                    pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 
>> CMD */
>> +                    drive-open-drain;
>> +                    slew-rate = <2>;
>> +                };
>> +            };
>> +
>> +            sdio_pins_b: sdio_pins_b@0 {
>> +                pins {
>> +                    pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 
>> D0 */
>> +                         <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
>> +                         <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
>> +                         <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
>> +                         <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
>> +                         <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
>> +                    drive-push-pull;
>> +                    slew-rate = <2>;
>> +                };
>> +            };
>> +
>> +            sdio_pins_od_b: sdio_pins_od_b@0 {
>> +                pins1 {
>> +                    pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 
>> D0 */
>> +                         <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
>> +                         <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
>> +                         <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
>> +                         <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
>> +                    drive-push-pull;
>> +                    slew-rate = <2>;
>> +                };
>> +
>> +                pins2 {
>> +                    pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 
>> CMD */
>> +                    drive-open-drain;
>> +                    slew-rate = <2>;
>> +                };
>> +            };
>>           };
>>       };
>>   };
>>