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Date: Tue, 13 Mar 2018 14:57:51 -0700 From: Doug Anderson <dianders@...omium.org> To: Derek Basehore <dbasehore@...omium.org> Cc: LKML <linux-kernel@...r.kernel.org>, "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>, Linux ARM <linux-arm-kernel@...ts.infradead.org>, linux-clk <linux-clk@...r.kernel.org>, Heiko Stübner <heiko@...ech.de>, sboyd@...nel.org, Michael Turquette <mturquette@...libre.com> Subject: Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate Hi, On Tue, Mar 13, 2018 at 1:37 PM, Derek Basehore <dbasehore@...omium.org> wrote: > We need this rate to generate 100, 200, and 228.57MHz from the same > PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for > and external display. > > Signed-off-by: Derek Basehore <dbasehore@...omium.org> > --- > drivers/clk/rockchip/clk-rk3399.c | 1 + > 1 file changed, 1 insertion(+) Looks good to me. I spent a little bit of time poking at this and I agreed it's the best way to make 1.6 GHz in <http://crosreview.com/956677>. Lin Huang at Rockchip also said: > yes, we also use this setting for 1.6GHz in our internal branch. ...and they seem to agree this is a sane setting. Thus: Reviewed-by: Douglas Anderson <dianders@...omium.org>
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