linux-kernel - Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Tue, 3 Apr 2018 15:58:38 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Linus Torvalds <torvalds@...ux-foundation.org>
Cc:     Greentime Hu <green.hu@...il.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Greentime <greentime@...estech.com>
Subject: Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

On Mon, Apr 2, 2018 at 6:04 PM, Linus Torvalds
<torvalds@...ux-foundation.org> wrote:
> On Sun, Apr 1, 2018 at 11:01 PM, Greentime Hu <green.hu@...il.com> wrote:
>>
>> This tag contains the core nds32 Linux port(including interrupt controller
>> driver and timer driver), which has been through 7 rounds of review on mailing
>> list.
>
> Can I get an overview of the nds32 architecture (uses, quirks, reasons
> for existing?) to add to the initial merge message? Just an overview,
> not some kind of architecture manual thing.
>
> Yeah, yeah, I can google it myself and write something up, but it's
> the kind of information I'd like to see when merging an architecture I
> hadn't really ever heard about, and I suspect most others haven't
> either.

The non-marketing description is that this is a fairly conventional
(in a good way) low-end RISC architecture that is usually integrated
into custom microcontroller and SoC designs, competing with
the similar ARM32, ARC, MIPS32, RISC-V, Xtensa and (currently
under review) C-Sky architectures that occupy the same space.

The most interesting bit from my perspective is that Andestech
are already selling a new generation of CPU cores that are
based on 32-bit and 64-bit RISC-V, but are still supporting enough
customers on the existing cores to invest in both.

     Arnd