| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Mon, 16 Apr 2018 19:57:42 +0200
From: Jerome Brunet <jbrunet@...libre.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Russell King <linux@...linux.org.uk>
Cc: Jerome Brunet <jbrunet@...libre.com>, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 2/3] clk: gate: add duty cycle passthrough ops
A clock gate does not resample the clock signal, it give the same
signal as the parent if enabled, so it can use the duty cycle
passthrough operations
Signed-off-by: Jerome Brunet <jbrunet@...libre.com>
---
drivers/clk/clk-gate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index dd82485e09a1..eb6dcebfcd5c 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -107,6 +107,8 @@ const struct clk_ops clk_gate_ops = {
.enable = clk_gate_enable,
.disable = clk_gate_disable,
.is_enabled = clk_gate_is_enabled,
+ .set_duty_cycle = __clk_set_duty_cycle_passthrough,
+ .get_duty_cycle = __clk_get_duty_cycle_passthrough,
};
EXPORT_SYMBOL_GPL(clk_gate_ops);
--
2.14.3
Powered by blists - more mailing lists