linux-kernel - Re: [PATCH] checkpatch: Add a --strict test for structs with bool member definitions

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Date:   Thu, 19 Apr 2018 06:40:56 +0200 (CEST)
From:   Julia Lawall <julia.lawall@...6.fr>
To:     Joe Perches <joe@...ches.com>
cc:     yuankuiz@...eaurora.org, Julia Lawall <julia.lawall@...6.fr>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Peter Zijlstra <peterz@...radead.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Andy Whitcroft <apw@...onical.com>,
        Linux PM <linux-pm@...r.kernel.org>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Frederic Weisbecker <fweisbec@...il.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        paulmck@...ux.vnet.ibm.com, Ingo Molnar <mingo@...nel.org>,
        Len Brown <len.brown@...el.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-pm-owner@...r.kernel.org
Subject: Re: [PATCH] checkpatch: Add a --strict test for structs with bool
 member definitions



On Wed, 18 Apr 2018, Joe Perches wrote:

> On Tue, 2018-04-17 at 17:07 +0800, yuankuiz@...eaurora.org wrote:
> > Hi julia,
> >
> > On 2018-04-15 05:19 AM, Julia Lawall wrote:
> > > On Wed, 11 Apr 2018, Joe Perches wrote:
> > >
> > > > On Thu, 2018-04-12 at 08:22 +0200, Julia Lawall wrote:
> > > > > On Wed, 11 Apr 2018, Joe Perches wrote:
> > > > > > On Wed, 2018-04-11 at 09:29 -0700, Andrew Morton wrote:
> > > > > > > We already have some 500 bools-in-structs
> > > > > >
> > > > > > I got at least triple that only in include/
> > > > > > so I expect there are at probably an order
> > > > > > of magnitude more than 500 in the kernel.
> > > > > >
> > > > > > I suppose some cocci script could count the
> > > > > > actual number of instances.  A regex can not.
> > > > >
> > > > > I got 12667.
> > > >
> > > > Could you please post the cocci script?
> > > >
> > > > > I'm not sure to understand the issue.  Will using a bitfield help if there
> > > > > are no other bitfields in the structure?
> > > >
> > > > IMO, not really.
> > > >
> > > > The primary issue is described by Linus here:
> > > > https://lkml.org/lkml/2017/11/21/384
> > > >
> > > > I personally do not find a significant issue with
> > > > uncontrolled sizes of bool in kernel structs as
> > > > all of the kernel structs are transitory and not
> > > > written out to storage.
> > > >
> > > > I suppose bool bitfields are also OK, but for the
> > > > RMW required.
> > > >
> > > > Using unsigned int :1 bitfield instead of bool :1
> > > > has the negative of truncation so that the uint
> > > > has to be set with !! instead of a simple assign.
> > >
> > > At least with gcc 5.4.0, a number of structures become larger with
> > > unsigned int :1. bool:1 seems to mostly solve this problem.  The
> > > structure
> > > ichx_desc, defined in drivers/gpio/gpio-ich.c seems to become larger
> > > with
> > > both approaches.
> >
> > [ZJ] Hopefully, this could make it better in your environment.
> >       IMHO, this is just for double check.
>
> I doubt this is actually better or smaller code.
>
> Check the actual object code using objdump and the
> struct alignment using pahole.

I didn't have a chance to try it, but it looks quite likely to result in a
smaller data structure based on the other examples that I looked at.

julia

>
> > diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
> > index 4f6d643..b46e170 100644
> > --- a/drivers/gpio/gpio-ich.c
> > +++ b/drivers/gpio/gpio-ich.c
> > @@ -70,6 +70,18 @@ static const u8 avoton_reglen[3] = {
> >   #define ICHX_READ(reg, base_res)       inl((reg) + (base_res)->start)
> >
> >   struct ichx_desc {
> > +       /* GPO_BLINK is available on this chipset */
> > +       bool uses_gpe0:1;
> > +
> > +       /* Whether the chipset has GPIO in GPE0_STS in the PM IO region
> > */
> > +        bool uses_gpe0:1;
> > +
> > +        /*
> > +         * Some chipsets don't let reading output values on GPIO_LVL
> > register
> > +         * this option allows driver caching written output values
> > +         */
> > +        bool use_outlvl_cache:1;
> > +
> >          /* Max GPIO pins the chipset can have */
> >          uint ngpio;
> >
> > @@ -77,24 +89,12 @@ struct ichx_desc {
> >          const u8 (*regs)[3];
> >          const u8 *reglen;
> >
> > -       /* GPO_BLINK is available on this chipset */
> > -       bool have_blink;
> > -
> > -       /* Whether the chipset has GPIO in GPE0_STS in the PM IO region
> > */
> > -       bool uses_gpe0;
> > -
> >          /* USE_SEL is bogus on some chipsets, eg 3100 */
> >          u32 use_sel_ignore[3];
> >
> >          /* Some chipsets have quirks, let these use their own
> > request/get */
> >          int (*request)(struct gpio_chip *chip, unsigned offset);
> >          int (*get)(struct gpio_chip *chip, unsigned offset);
> > -
> > -       /*
> > -        * Some chipsets don't let reading output values on GPIO_LVL
> > register
> > -        * this option allows driver caching written output values
> > -        */
> > -       bool use_outlvl_cache;
> >   };
> >
> >
> > ZJ
>