linux-kernel - Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Date:   Wed, 2 May 2018 18:02:12 +0800
From:   David Wang <davidwang@...oxin.com>
To:     'Borislav Petkov' <bp@...en8.de>
CC:     <tony.luck@...el.com>, <tglx@...utronix.de>, <mingo@...hat.com>,
        <hpa@...or.com>, <gregkh@...uxfoundation.org>, <x86@...nel.org>,
        <linux-kernel@...r.kernel.org>, <linux-edac@...r.kernel.org>,
        <brucechang@...-alliance.com>, <cooperyan@...oxin.com>,
        <qiyuanwang@...oxin.com>, <benjaminpan@...tech.com>,
        <lukelin@...cpu.com>, <timguo@...oxin.com>
Subject: Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs



> -----Original Mail-----
> Sender: Borislav Petkov [mailto:bp@...en8.de]
> Time: 2018年4月30日 17:48
> Receiver: David Wang <davidwang@...oxin.com>
> CC: tony.luck@...el.com; tglx@...utronix.de; mingo@...hat.com;
> hpa@...or.com; gregkh@...uxfoundation.org; x86@...nel.org; linux-
> kernel@...r.kernel.org; linux-edac@...r.kernel.org; brucechang@...-
> alliance.com; cooperyan@...oxin.com; qiyuanwang@...oxin.com;
> benjaminpan@...tech.com; lukelin@...cpu.com; timguo@...oxin.com
> Subject: Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs
> 
> On Wed, Apr 25, 2018 at 06:33:40PM +0800, David Wang wrote:
> > Newer Centaur support CMCI mechnism, which is compatible with INTEL
> CMCI.
> >
> > Signed-off-by: David Wang <davidwang@...oxin.com>
> > ---
> >  arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c
> > b/arch/x86/kernel/cpu/mcheck/mce.c
> > index 38ccab8..f9a7295 100644
> > --- a/arch/x86/kernel/cpu/mcheck/mce.c
> > +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> > @@ -1757,6 +1757,8 @@ static void __mcheck_cpu_init_vendor(struct
> cpuinfo_x86 *c)
> >  		}
> >  	case X86_VENDOR_CENTAUR:
> >  		mce_centaur_feature_init(c);
> > +		mce_intel_feature_init(c);
> > +		mce_adjust_timer = cmci_intel_adjust_timer;
> 
> This won't work in configs with CONFIG_X86_MCE_INTEL disabled.
> 
> You need to define CONFIG_X86_MCE_CENTAUR or so which depends on
> CONFIG_CPU_SUP_CENTAUR and CONFIG_X86_MCE_INTEL and which then
> makes sure the intel CMCI et al stuff is enabled.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> Good mailing practices for 400: avoid top-posting and trim the reply.

	OK. I got it.
	I will send another patch.
	Thank you.

---
David