linux-kernel - [PATCH] mtd: spi-nor: add support for Microchip 25LC256

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 4 May 2018 18:54:04 +0300
From:   Radu Pirea <radu.pirea@...rochip.com>
To:     <linux-kernel@...r.kernel.org>, <linux-mtd@...ts.infradead.org>
CC:     <Zhiqiang.Hou@....com>, <pp@...ix.com>, <richard@....at>,
        <boris.brezillon@...tlin.com>, <computersforpeace@...il.com>,
        <dwmw2@...radead.org>, <marek.vasut@...il.com>,
        Radu Pirea <radu.pirea@...rochip.com>
Subject: [PATCH] mtd: spi-nor: add support for Microchip 25LC256

Added geometry description for Microchip 25LC256 memory.

Signed-off-by: Radu Pirea <radu.pirea@...rochip.com>
---
 drivers/mtd/devices/m25p80.c  | 3 +++
 drivers/mtd/spi-nor/spi-nor.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index a4e18f6aaa33..1e359d811261 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
 
+	/* Microchip */
+	{ "25lc256" },
+
 	{ },
 };
 MODULE_DEVICE_TABLE(spi, m25p_ids);
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index d445a4d3b770..6341c86be647 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
 
+	/* Microchip */
+	{ "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+
 	/* Micron */
 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
-- 
2.16.2