linux-kernel - Re: [PATCH v6 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SDM845

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Date:   Mon, 07 May 2018 16:12:49 +0530
From:   Amit Nischal <anischal@...eaurora.org>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Odelu Kukatla <okukatla@...eaurora.org>,
        Taniya Das <tdas@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-clk-owner@...r.kernel.org
Subject: Re: [PATCH v6 3/3] clk: qcom: Add Global Clock controller (GCC)
 driver for SDM845

On 2018-05-05 08:44, Stephen Boyd wrote:
> Quoting Amit Nischal (2018-05-04 03:45:12)
>> On 2018-05-02 12:53, Stephen Boyd wrote:
>> > Quoting Amit Nischal (2018-04-30 09:20:10)
>> >> +
>> >> +static struct clk_branch gcc_disp_gpll0_clk_src = {
>> >> +       .halt_reg = 0x52004,
>> >> +       .halt_check = BRANCH_HALT_DELAY,
>> >
>> > What about this one? It's not a phy so I'm confused again why we're
>> > unable to check the halt bit. To be clear(er), I don't see why we ever
>> > want to have HALT_DELAY used. Hopefully we can remove that flag.
>> >
>> > From what I recall, the flag is there for clks that don't toggle their
>> > status bit at all, but that we know take a few cycles to ungate the
>> > upstream clk. So we threw a delay into the code to make sure that when
>> > clk_enable() returned, a driver wouldn't try to use hardware before the
>> > clk was actually on. But these cases should pretty much never happen,
>> > hence all the pushback against this flag.
>> >
>> 
>> For these "*gpll0_clk_src" and "*gpll0_div_clk" clocks, there is no 
>> halt
>> bit to check the status and it is required to have delay for few 
>> cycles
>> so that clock gets turned on before a client driver to use the 
>> hardware.
> 
> Ok.. but then why is there a 'halt_reg' configured for the clk?

Thanks for the review.
I will remove the halt_reg for the clocks where we are using the 
'HALT_DELAY'
flag and there is no need to poll the status bit as we are returning 
early
from the 'clk_branch_wait()' function.

> 
>> >> +
>> >> +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
>> >> +       .halt_reg = 0x75018,
>> >> +       .halt_check = BRANCH_HALT_DELAY,
>> >
>> > There are still HALT_DELAY flags for UFS though? Why?
>> 
>> For ufs_card tx/rx symbol clocks, we don't poll the status bit as
>> per the recommendation from the HW team. We can change the halt_check
>> type to newly implemented flag "BRANCH_HALT_SKIP". Please update us 
>> with
>> your thoughts to change the flag to "BRANCH_HALT_SKIP".
> 
> Yes use HALT_SKIP please.

Thanks for confirming. I will do the changes in the next patch series.

> 
>> 
>> >
>> > Also, are you going to send DFS support for the QUP clks? I would like
>> > to see that code merged soon.
>> 
>> Taniya has sent the patches for DFS support for QUP clocks.
>> https://patchwork.kernel.org/patch/10376951/
>> 
> 
> I'll take a look.
> --
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