linux-kernel - Re: [linux-sunxi] [PATCH v2 2/4] ARM: dtsi: add pwm node for sun8i.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Tue, 15 May 2018 00:08:57 +0800
From:   Hao Zhang <hao5781286@...il.com>
To:     André Przywara <andre.przywara@....com>
Cc:     Thierry Reding <thierry.reding@...il.com>, robh+dt@...nel.org,
        Mark Rutland <mark.rutland@....com>,
        Chen-Yu Tsai <wens@...e.org>,
        Maxime Ripard <maxime.ripard@...e-electrons.com>,
        linux@...linux.org.uk, linux-gpio@...r.kernel.org,
        open list <linux-kernel@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/Allwinner sunXi SoC support" 
        <linux-arm-kernel@...ts.infradead.org>, linux-pwm@...r.kernel.org,
        linux-sunxi@...glegroups.com
Subject: Re: [linux-sunxi] [PATCH v2 2/4] ARM: dtsi: add pwm node for sun8i.

2018-02-28 9:53 GMT+08:00 André Przywara <andre.przywara@....com>:
> Hi,
>
> The subject line should mention the R40, there are far too many sun8i SoCs.

Okey.

>
> On 25/02/18 13:51, hao_zhang wrote:
>> This patch adds pwm node for sun8i.
>>
>> Signed-off-by: hao_zhang <hao5781286@...il.com>
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 13 +++++++++++++
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
>> index 173dcc1..99a0261 100644
>> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -295,6 +295,11 @@
>>                               bias-pull-up;
>>                       };
>>
>> +                     pwm_ch0_pin: pwm-ch0-pin {
>> +                             pins = "PB2";
>> +                             function = "pwm";
>> +                     };
>> +
>>                       uart0_pb_pins: uart0-pb-pins {
>>                               pins = "PB22", "PB23";
>>                               function = "uart0";
>> @@ -306,6 +311,14 @@
>>                       reg = <0x01c20c90 0x10>;
>>               };
>>
>> +             pwm: pwm@...3400 {
>> +                          compatible = "allwinner,sun8i-r40-pwm";
>> +                          reg = <0x01c23400 0x154>;
>
> Following my comments on the binding document:
>                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>
>> +                          clocks = <&osc24M>;
>
> And possibly multiple clocks here (though I fail to find the APB1 clock
> being exposed by our CCU).

It seem CCU dosen't support APB1 clock for R40 PWM...

>
> Cheers,
> Andre.
>
>> +                          #pwm-cells = <3>;
>> +                          status = "disabled";
>> +             };
>> +
>>               uart0: serial@...8000 {
>>                       compatible = "snps,dw-apb-uart";
>>                       reg = <0x01c28000 0x400>;
>>
>