linux-kernel - Re: [PATCH v2 12/16] dt-bindings/interrupt-controller: update Marvell ICU bindings

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Date:   Fri, 8 Jun 2018 16:00:58 +0200
From:   Miquel Raynal <miquel.raynal@...tlin.com>
To:     Rob Herring <robh@...nel.org>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <marc.zyngier@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Andrew Lunn <andrew@...n.ch>,
        Gregory Clement <gregory.clement@...tlin.com>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Mark Rutland <mark.rutland@....com>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Antoine Tenart <antoine.tenart@...tlin.com>,
        Maxime Chevallier <maxime.chevallier@...tlin.com>,
        Nadav Haklai <nadavh@...vell.com>,
        Haim Boot <hayim@...vell.com>, Hanna Hawa <hannah@...vell.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 12/16] dt-bindings/interrupt-controller: update
 Marvell ICU bindings

Hi Rob,

Thanks for reviewing.

On Tue, 5 Jun 2018 14:29:02 -0600, Rob Herring <robh@...nel.org> wrote:

> On Tue, May 22, 2018 at 11:40:38AM +0200, Miquel Raynal wrote:
> > Change the documentation to reflect the new bindings used for Marvell
> > ICU. This involves describing each interrupt group as a subnode of the
> > ICU node. Each of them having their own compatible.  
> 
> Need to explain why you need to do this and why breaking backwards 
> compatibility is okay.

As explained by Thomas, backward compatibility is not broken as old
bindings are still documented and supported.

I will update the commit message to reflect that point.

> 
> > 
> > Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>
> > ---
> >  .../bindings/interrupt-controller/marvell,icu.txt  | 81 ++++++++++++++++++----
> >  1 file changed, 69 insertions(+), 12 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
> > index 649b7ec9d9b1..6f7e4355b3d8 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
> > @@ -5,6 +5,8 @@ The Marvell ICU (Interrupt Consolidation Unit) controller is
> >  responsible for collecting all wired-interrupt sources in the CP and
> >  communicating them to the GIC in the AP, the unit translates interrupt
> >  requests on input wires to MSG memory mapped transactions to the GIC.
> > +These messages will access a different GIC memory area depending on
> > +their type (NSR, SR, SEI, REI, etc).
> >  
> >  Required properties:
> >  
> > @@ -12,20 +14,19 @@ Required properties:
> >  
> >  - reg: Should contain ICU registers location and length.
> >  
> > +Subnodes: Each group of interrupt is declared as a subnode of the ICU,
> > +with their own compatible.
> > +
> > +Required properties for the icu_nsr/icu_sei subnodes:
> > +
> > +- compatible: Should be "marvell,cp110-icu-nsr" or "marvell,cp110-icu-sei".
> > +
> >  - #interrupt-cells: Specifies the number of cells needed to encode an
> > -  interrupt source. The value shall be 3.
> > +  interrupt source. The value shall be 2.
> >  
> > -  The 1st cell is the group type of the ICU interrupt. Possible group
> > -  types are:
> > +  The 1st cell is the index of the interrupt in the ICU unit.
> >  
> > -   ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
> > -   ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure
> > -   ICU_GRP_SEI (0x4) : System error interrupt
> > -   ICU_GRP_REI (0x5) : RAM error interrupt  
> 
> What happens to SR and REI interrupts?

They were unused since the beginning.

These values are still detailed below (in the legacy section).

[...]

> 
> > -
> > -  The 2nd cell is the index of the interrupt in the ICU unit.
> > -
> > -  The 3rd cell is the type of the interrupt. See arm,gic.txt for
> > +  The 2nd cell is the type of the interrupt. See arm,gic.txt for
> >    details.
> >  
> >  - interrupt-controller: Identifies the node as an interrupt
> > @@ -35,17 +36,73 @@ Required properties:
> >    that allows to trigger interrupts using MSG memory mapped
> >    transactions.
> >  
> > +Note: each 'interrupts' property referring to any 'icu_xxx' node shall
> > +      have a different number within [0:206].
> > +
> >  Example:
> >  
> >  icu: interrupt-controller@...000 {
> >  	compatible = "marvell,cp110-icu";
> >  	reg = <0x1e0000 0x440>;
> > +
> > +	CP110_LABEL(icu_nsr): icu-nsr {  
> 
> 'interrupt-controller' is the proper node name. Is there no register 
> range associated sub nodes?

I will update the name.

A few are used only for NSR, a few only for SEI and others are used for
both. But ok, I will add register ranges.

> 
> > +		compatible = "marvell,cp110-icu-nsr";
> > +		#interrupt-cells = <2>;
> > +		interrupt-controller;
> > +		msi-parent = <&gicp>;
> > +	};
> > +
> > +        CP110_LABEL(icu_sei): icu-sei {
> > +                compatible = "marvell,cp110-icu-sei";
> > +                #interrupt-cells = <2>;
> > +                interrupt-controller;
> > +                msi-parent = <&sei>;
> > +        };  
> 
> Mixture of tabs and spaces.

Oops.

> 
> > +};
> > +

Thanks,
Miquèl