linux-kernel - RE: [PATCH v9 10/12] KVM: x86: Implement Intel Processor Trace MSRs read/write emulation

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Date:   Fri, 8 Jun 2018 15:12:36 +0000
From:   "Kang, Luwei" <luwei.kang@...el.com>
To:     Alexander Shishkin <alexander.shishkin@...ux.intel.com>
CC:     "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "chao.p.peng@...ux.intel.com" <chao.p.peng@...ux.intel.com>,
        "thomas.lendacky@....com" <thomas.lendacky@....com>,
        "bp@...e.de" <bp@...e.de>, "Liang, Kan" <kan.liang@...el.com>,
        "Janakarajan.Natarajan@....com" <Janakarajan.Natarajan@....com>,
        "dwmw@...zon.co.uk" <dwmw@...zon.co.uk>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "mathieu.poirier@...aro.org" <mathieu.poirier@...aro.org>,
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        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "rkrcmar@...hat.com" <rkrcmar@...hat.com>,
        "david@...hat.com" <david@...hat.com>,
        "bsd@...hat.com" <bsd@...hat.com>,
        "yu.c.zhang@...ux.intel.com" <yu.c.zhang@...ux.intel.com>,
        "joro@...tes.org" <joro@...tes.org>
Subject: RE: [PATCH v9 10/12] KVM: x86: Implement Intel Processor Trace MSRs
 read/write emulation

> > +	/*
> > +	 * Any MSR write that attempts to change bits marked reserved will
> > +	 * case a #GP fault.
> > +	 */
> > +	if (data & vmx->pt_desc.ctl_bitmask)
> > +		return 1;
> > +
> > +	/*
> > +	 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
> > +	 * result in a #GP unless the same write also clears TraceEn.
> > +	 */
> > +	if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
> > +		((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
> > +		return 1;
> > +
> > +	/*
> > +	 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
> > +	 * and FabricEn would cause #GP, if
> > +	 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
> > +	 */
> > +	if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
> > +		!(data & RTIT_CTL_FABRIC_EN) &&
> > +		!pt_cap_decode(vmx->pt_desc.caps,
> PT_CAP_single_range_output))
> > +		return 1;
> 
> Ah, I see. But afaict this is still wrong: PT_CAP_single_range_output is only  about allowing !RTIT_CTL_TOPA, 

This is follow the description in SDM (35.2.7.2 IA32_RTIT_CTL MSR   -> ToPA -> Note:...)

> FABRIC_EN should be checked separately against the new capability that you added in 4/12.

Yes, it have has been handled in patch 9.
+       /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
+       if (pt_cap_decode(vmx->pt_desc.caps, PT_CAP_output_subsys))
+               vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;

Thanks,
Luwei Kang