linux-kernel - Re: [RFC PATCH 00/16] x86/split_lock: Enable #AC exception for split locked accesses

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Date:   Thu, 21 Jun 2018 13:18:52 -0700
From:   Fenghua Yu <fenghua.yu@...el.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     Fenghua Yu <fenghua.yu@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...e.hu>,
        "H. Peter Anvin" <hpa@...ux.intel.com>,
        Ashok Raj <ashok.raj@...el.com>,
        Dave Hansen <dave.hansen@...el.com>,
        Rafael Wysocki <rafael.j.wysocki@...el.com>,
        Tony Luck <tony.luck@...el.com>,
        Alan Cox <alan@...ux.intel.com>,
        Ravi V Shankar <ravi.v.shankar@...el.com>,
        Arjan van de Ven <arjan@...radead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [RFC PATCH 00/16] x86/split_lock: Enable #AC exception for split
 locked accesses

On Thu, Jun 21, 2018 at 09:37:38PM +0200, Peter Zijlstra wrote:
> On Sun, May 27, 2018 at 08:45:49AM -0700, Fenghua Yu wrote:
> > Currently we can trace split lock event counter for debug purpose. But
> 
> How? A while ago I actually tried that, but I could not find a suitable
> perf event.

The event name is called sq_misc.split_lock. It's been supported in perf
already.

> 
> > Intel introduces mechanism to detect split lock via alignment
> > check exception in Tremont and other future processors. If split lock is
> > from user process, #AC handler can kill the process or re-execute faulting
> > instruction depending on configuration. 
> 
> Ideally it would #AC any unaligned (implied) LOCK prefix instruction,
> not just across lines.

This feature only triggers #AC for unaligned cache line access, not for
other aligned (4 bytes, 8 bytes, etc). This is not explicitly said in
ISE. I can add this info in next version of patches.

> 
> > To detect split lock, a new control bit (bit 29) in per-core TEST_CTL
> > MSR 0x33 will be introduced in future x86 processors. When the bit 29
> > is set, the processor causes #AC exception for split locked accesses at
> > all CPL.
> 
> Per-Core is really unfortunate, but better than nothing.

Agree with you! Per-core is at least for current hardware implementation.
The code and locking in the code are supposed to work in the future on
potential per-thread or even per-socket implmentation.

Thanks.

-Fenghua