linux-kernel - [PATCH 2/2] clk: ingenic: Add missing flag for UDC clock

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Date:   Wed, 27 Jun 2018 14:14:59 +0200
From:   Paul Cercueil <paul@...pouillou.net>
To:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>
Cc:     Paul Burton <paul.burton@...s.com>,
        James Hogan <jhogan@...nel.org>, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, Paul Cercueil <paul@...pouillou.net>
Subject: [PATCH 2/2] clk: ingenic: Add missing flag for UDC clock

The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.

Signed-off-by: Paul Cercueil <paul@...pouillou.net>
---
 drivers/clk/ingenic/jz4740-cgu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index bc073dd4470d..4479c102e899 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -161,7 +161,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
 	},
 
 	[JZ4740_CLK_UDC] = {
-		"udc", CGU_CLK_MUX | CGU_CLK_DIV,
+		"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
 		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
 		.mux = { CGU_REG_CPCCR, 29, 1 },
 		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
-- 
2.11.0