[82] = "Cts_ge2d_clk ", [81] = "Cts_vapbclk ", [80] = "Rng_ring_osc_clk[3]", [79] = "Rng_ring_osc_clk[2]", [78] = "Rng_ring_osc_clk[1]", [77] = "Rng_ring_osc_clk[0]", [76] = "cts_aoclk_int ", [75] = "cts_aoclkx2_int ", [74] = "0 ", [73] = "cts_pwm_C_clk ", [72] = "cts_pwm_D_clk ", [71] = "cts_pwm_E_clk ", [70] = "cts_pwm_F_clk ", [69] = "0 ", [68] = "0 ", [67] = "0 ", [66] = "cts_vid_lock_clk ", [65] = "0 ", [64] = "0 ", [63] = "0 ", [62] = "cts_hevc_clk ", [61] = "gpio_clk_msr ", [60] = "alt_32k_clk ", [59] = "cts_hcodec_clk ", [58] = "cts_wave420l_bclk ", [57] = "cts_wave420l_cclk ", [56] = "cts_cci_clk ", [55] = "vid_pll_div_clk_out ", [54] = "0 ", [53] = "Sd_emmc_clk_A ", [52] = "Sd_emmc_clk_B ", [51] = "Cts_nand_core_clk ", [50] = "Mp3_clk_out ", [49] = "mp2_clk_out ", [48] = "mp1_clk_out ", [47] = "ddr_dpll_pt_clk ", [46] = "cts_vpu_clk ", [45] = "cts_pwm_A_clk ", [44] = "cts_pwm_B_clk ", [43] = "fclk_div5 ", [42] = "mp0_clk_out ", [41] = "eth_rx_clk_or_clk_rmii", [40] = "cts_pcm_mclk ", [39] = "cts_pcm_sclk ", [38] = "cts_vdin_meas_clk ", [37] = "cts_clk_i958 ", [36] = "cts_hdmi_tx_pixel_clk ", [35] = "cts_mali_clk ", [34] = "0 ", [33] = "0 ", [32] = "cts_vdec_clk ", [31] = "MPLL_CLK_TEST_OUT ", [30] = "0 ", [29] = "0 ", [28] = "cts_sar_adc_clk ", [27] = "0 ", [26] = "sc_clk_int ", [25] = "0 ", [24] = "sys_cpu1_clk_div16 ", [23] = "HDMI_CLK_TODIG ", [22] = "eth_phy_ref_clk ", [21] = "i2s_clk_in_src0 ", [20] = "rtc_osc_clk_out ", [19] = "cts_hdmitx_sys_clk ", [18] = "sys_cpu_clk_div16 ", [17] = "sys_pll_div16 ", [16] = "cts_FEC_CLK_2 ", [15] = "cts_FEC_CLK_1 ", [14] = "cts_FEC_CLK_0 ", [13] = "cts_amclk ", [12] = "Cts_pdm_clk ", [11] = "mac_eth_tx_clk ", [10] = "cts_vdac_clk ", [9] = "cts_encl_clk ", [8] = "cts_encp_clk ", [7] = "clk81 ", [6] = "cts_enci_clk ", [5] = "0 ", [4] = "gp0_pll_clk ", [3] = "A53_ring_osc_clk ", [2] = "am_ring_osc_clk_out_ee[2]", [1] = "am_ring_osc_clk_out_ee[1]", [0] = "am_ring_osc_clk_out_ee[0]",