Date:   Wed, 18 Jul 2018 15:25:31 -0600
From:   Alex Williamson <alex.williamson@...hat.com>
To:     Srinath Mannam <srinath.mannam@...adcom.com>
Cc:     Ray Jui <ray.jui@...adcom.com>,
        Vikram Prakash <vikram.prakash@...adcom.com>,
        Scott Branden <scott.branden@...adcom.com>,
        kvm@...r.kernel.org,
        BCM Kernel Feedback <bcm-kernel-feedback-list@...adcom.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        aik@...abs.ru, David Gibson <david@...son.dropbear.id.au>,
        benh@...nel.crashing.org
Subject: Re: [RFC PATCH] vfio/pci: map prefetchble bars as writecombine

On Thu, 19 Jul 2018 00:05:18 +0530
Srinath Mannam <srinath.mannam@...adcom.com> wrote:

> Hi Alex,
> 
> On Tue, Jul 17, 2018 at 8:52 PM, Alex Williamson
> <alex.williamson@...hat.com> wrote:
> > On Fri, 13 Jul 2018 10:26:17 +0530
> > Srinath Mannam <srinath.mannam@...adcom.com> wrote:
> >  
> >> By default all BARs map with VMA access permissions
> >> as pgprot_noncached.
> >>
> >> In ARM64 pgprot_noncached is MT_DEVICE_nGnRnE which
> >> is strongly ordered and allows aligned access.
> >> This type of mapping works for NON-PREFETCHABLE bars
> >> containing EP controller registers.
> >> But it restricts PREFETCHABLE bars from doing
> >> unaligned access.
> >>
> >> In CMB NVMe drives PREFETCHABLE bars are required to
> >> map as MT_NORMAL_NC to do unaligned access.
> >>
> >> Signed-off-by: Srinath Mannam <srinath.mannam@...adcom.com>
> >> Reviewed-by: Ray Jui <ray.jui@...adcom.com>
> >> Reviewed-by: Vikram Prakash <vikram.prakash@...adcom.com>
> >> ---  
> >
> > This has been discussed before:
> >
> > https://www.spinics.net/lists/kvm/msg156548.html  
> Thank you for inputs.. I have gone through the long list of mail chain
> discussion.
> >
> > CC'ing the usual suspects from the previous thread.  I'm not convinced
> > that the patch here has considered anything other than the ARM64
> > implications and it's not clear that it considers compatibility with
> > existing users or devices at all.  Can we guarantee for all devices and
> > use cases that WC is semantically equivalent and preferable to UC?  If
> > not then we need to device an extension to the interface that allows
> > the user to specify WC.  Thanks,
> >  
> To implement with user specified WC flags, many changes need to be done.
> Suppose In DPDK, prefetcable BARs map using WC flag, then also same
> question comes
> that WC may be different for different CPUs.
> As per functionality, both WC and PREFETCHABLE are same, like merging writes and
> typically WC is uncached.
> So, based on prefetchable BARs behavior and usage we need to map bar memory.
> Is it right to map prefetchable BARs as strongly ordered, aligned
> access and uncached?

Is it possible to answer that question generically?  Whether to map a
BAR as UC or WC is generally a question for the driver.  Does the
device handle unaligned accesses?  Does the device need strong memory
ordering?  If this is a driver level question then the driver that
needs to make that decision is the userspace driver.  VFIO is just a
pass-through here and since we don't offer the user a choice of
mappings, we take the safer and more conservative mapping, ie. UC.

You're suggesting that there are many changes to be done if we modify
the vfio interface to expose WC under the user's control rather than
simply transparently impose WC for all mappings, but is that really the
case?  Most devices on most platforms seem to work fine now.  Perhaps WC
is a performance optimization, but this is the first instance I've seen
of it as a functional issue.  Does that suggest that the imposed
alignment on your platform is perhaps unique and the relaxed alignment
should be implemented at the architecture specific memory flags for UC
mappings?  For instance, does x86 require this change for the same
device?  The chance for regressions of other devices on other platforms
seems rather high as proposed. Thanks,

Alex

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