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Date:   Mon, 23 Jul 2018 11:43:56 -0400
From:   "Liang, Kan" <kan.liang@...ux.intel.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     tglx@...utronix.de, mingo@...hat.com, linux-kernel@...r.kernel.org,
        acme@...nel.org, alexander.shishkin@...ux.intel.com,
        vincent.weaver@...ne.edu, jolsa@...hat.com, ak@...ux.intel.com
Subject: Re: [PATCH 1/4] x86/perf/intel: Introduce PMU flag for Extended PEBS



On 7/23/2018 11:16 AM, Peter Zijlstra wrote:
> On Thu, Mar 08, 2018 at 06:15:39PM -0800, kan.liang@...ux.intel.com wrote:
>> From: Kan Liang <kan.liang@...ux.intel.com>
>>
>> The Extended PEBS feature, introduced in Goldmont Plus
>> microarchitecture, supports all events as "Extended PEBS".
>>
>> Introduce flag PMU_FL_PEBS_ALL to indicate the platforms which support
>> extended PEBS.
>> To support all events, it needs to support all constraints for PEBS. To
>> avoid duplicating all the constraints in the PEBS table, making the PEBS
>> code search the normal constraints too.
>>
> 
> So I like PEBS_ALL.. what I don't like is that it seems to be mutually
> exclusive with PEBS Load Latency.

Right, MSR_PEBS_ENABLE:32-35 is model specific.
For Atom,
   Goldmont and earlier platform, they are reserved.
   Goldmont Plus, 32-34 are for fixed counter, 35 is reserved.
For Core,
   from Nehalem to latest 8th, 32-35 are for Load Latency.

> Took the patches.
Thanks.

Kan


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