linux-kernel - Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

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Date:   Sun, 18 Aug 2019 08:10:22 +0200
From:   Oleksij Rempel <linux@...pel-privat.de>
To:     Chuanhong Guo <gch981213@...il.com>
Cc:     Rob Herring <robh@...nel.org>,
        "open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:MIPS" <linux-mips@...r.kernel.org>,
        "open list:STAGING SUBSYSTEM" <devel@...verdev.osuosl.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Paul Burton <paul.burton@...s.com>,
        James Hogan <jhogan@...nel.org>,
        John Crispin <john@...ozen.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Weijie Gao <hackpascal@...il.com>, NeilBrown <neil@...wn.name>,
        Paul Fertser <fercerpav@...il.com>
Subject: Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding
 documentation

Am 18.08.19 um 04:29 schrieb Chuanhong Guo:
> Hi!
>
> On Sun, Aug 18, 2019 at 2:06 AM Oleksij Rempel <linux@...pel-privat.de> wrote:
>>>> SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks.
>>>> Jist wild assumption. All peripheral devices are suing bus clock.
>>>
>>> This assumption is incorrect. When this patchset is applied in
>>> OpenWrt, I asked the author why there's still a fixed clock in
>>> mt7621.dtsi, He told me that there's another clock for those unchanged
>>> peripherals and he doesn't have time to write a clock provider for it.
>>
>> Can you please provide a link to this patch or email.
>
> This discussion is in Chinese and using an IM software so there's no
> link available.
>
>> We have at least 2 know registers:
>> SYSC_REG_CPLL_CLKCFG0 - it provides some information about boostrapped
>> refclock. PLL and dividers used for CPU and some sort of BUS (AHB?).
>> SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for
>> all or some ip cores.
>> What is probably missing is a set of dividers for
>> each ip core. From your words it is not document.
>
> The specific missing part I was referring to, is parent clocks for
> every gates. I'm not going to assume this with current openwrt device
> tree because some peripherals doesn't have a clock binding at all or
> have a dummy one there.

Ok, then I do not understand what is the motivation to upstream
something what is not nearly ready for use. This code is currently on
prototyping phase and you have no information how to make it ready.

It means, we cannot expect that this driver will be fixed any time soon.

--
Regards,
Oleksij