linux-kernel - [PATCH AUTOSEL 4.19 01/33] MIPS: Ingenic: Disable broken BTB lookup optimization.

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Date:   Sun, 29 Sep 2019 13:33:49 -0400
From:   Sasha Levin <sashal@...nel.org>
To:     linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc:     Zhou Yanjie <zhouyanjie@...o.com>,
        Paul Burton <paul.burton@...s.com>, linux-mips@...r.kernel.org,
        ralf@...ux-mips.org, paul@...pouillou.net, jhogan@...nel.org,
        malat@...ian.org, gregkh@...uxfoundation.org, tglx@...utronix.de,
        allison@...utok.net, syq@...ian.org, chenhc@...ote.com,
        jiaxun.yang@...goat.com, Sasha Levin <sashal@...nel.org>
Subject: [PATCH AUTOSEL 4.19 01/33] MIPS: Ingenic: Disable broken BTB lookup optimization.

From: Zhou Yanjie <zhouyanjie@...o.com>

[ Upstream commit 053951dda71ecb4b554a2cdbe26f5f6f9bee9dd2 ]

In order to further reduce power consumption, the XBurst core
by default attempts to avoid branch target buffer lookups by
detecting & special casing loops. This feature will cause
BogoMIPS and lpj calculate in error. Set cp0 config7 bit 4 to
disable this feature.

Signed-off-by: Zhou Yanjie <zhouyanjie@...o.com>
Signed-off-by: Paul Burton <paul.burton@...s.com>
Cc: linux-mips@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: ralf@...ux-mips.org
Cc: paul@...pouillou.net
Cc: jhogan@...nel.org
Cc: malat@...ian.org
Cc: gregkh@...uxfoundation.org
Cc: tglx@...utronix.de
Cc: allison@...utok.net
Cc: syq@...ian.org
Cc: chenhc@...ote.com
Cc: jiaxun.yang@...goat.com
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 arch/mips/include/asm/mipsregs.h | 4 ++++
 arch/mips/kernel/cpu-probe.c     | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 01df9ad62fb83..1bb9448777c5c 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -688,6 +688,9 @@
 #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
 
+/* Ingenic Config7 bits */
+#define MIPS_CONF7_BTB_LOOP_EN	(_ULCAST_(1) << 4)
+
 /* Config7 Bits specific to MIPS Technologies. */
 
 /* Performance counters implemented Per TC */
@@ -2774,6 +2777,7 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(config5)
+__BUILD_SET_C0(config7)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d535fc706a8b3..25cd8737e7fe0 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1879,6 +1879,13 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 		c->cputype = CPU_JZRISC;
 		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 		__cpu_name[cpu] = "Ingenic JZRISC";
+		/*
+		 * The XBurst core by default attempts to avoid branch target
+		 * buffer lookups by detecting & special casing loops. This
+		 * feature will cause BogoMIPS and lpj calculate in error.
+		 * Set cp0 config7 bit 4 to disable this feature.
+		 */
+		set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
 		break;
 	default:
 		panic("Unknown Ingenic Processor ID!");
-- 
2.20.1