linux-kernel - Re: [PATCH v2 7/9] irqchip: Add RISC-V advanced PLIC driver

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Date:   Fri, 24 Nov 2023 03:15:01 +0000
From:   谢 波 <xiebo_60@...e.com>
To:     "apatel@...tanamicro.com" <apatel@...tanamicro.com>
CC:     "Alistair.Francis@....com" <Alistair.Francis@....com>,
        "anup@...infault.org" <anup@...infault.org>,
        "atishp@...shpatra.org" <atishp@...shpatra.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "maz@...nel.org" <maz@...nel.org>,
        "palmer@...belt.com" <palmer@...belt.com>,
        "paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>
Subject: Re: [PATCH v2 7/9] irqchip: Add RISC-V advanced PLIC driver

Hello all,

I have a question regarding the handling of potential issues during the MSI interrupt sending process. It appears that if the APLIC target register's value is modified during the MSI interrupt sending process, it could potentially lead to MSI interrupt send failures. The code doesn't seem to account for this scenario or take appropriate measures.

I am reaching out to seek clarification on whether this situation has been considered and if there are specific reasons for not addressing it in the code. Your insights into this matter would be highly appreciated.

Thank you for your time, and I look forward to your response.

Best regards