linux-kernel - Re: [PATCH v3 3/3] clk: mediatek: mt8188-topckgen: Refactor parents for top

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Date: Tue, 02 Jan 2024 16:51:40 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: mturquette@...libre.com, matthias.bgg@...il.com, angelogioacchino.delregno@...labora.com, wenst@...omium.org, msp@...libre.com, amergnat@...libre.com, yangyingliang@...wei.com, u.kleine-koenig@...gutronix.de, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH v3 3/3] clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes

Quoting AngeloGioacchino Del Regno (2023-11-03 03:25:33)
> The top_dp and top_edp muxes can be both parented to either TVDPLL1
> or TVDPLL2, two identically specced PLLs for the specific purpose of
> giving out pixel clock: this becomes a problem when the MediaTek
> DisplayPort Interface (DPI) driver tries to set the pixel clock rate.
> 
> In the usecase of two simultaneous outputs (using two controllers),
> it was seen that one of the displays would sometimes display garbled
> output (if any at all) and this was because:
>  - top_edp was set to TVDPLL1, outputting X GHz
>  - top_dp was set to TVDPLL2, outputting Y GHz
>    - mtk_dpi calls clk_set_rate(top_edp, Z GHz)
>  - top_dp is switched to TVDPLL1
>  - TVDPLL1 changes its rate, top_edp outputs the wrong rate.
>  - eDP display is garbled
> 
> To solve this issue, remove all TVDPLL1 parents from `top_dp` and
> all TVDPLL2 parents from `top_edp`, plus, necessarily switch both
> clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be
> able to use the right bit index for the new parents list.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---

Applied to clk-next