netdev - Re: [PATCH 3/7] NetXen: Multi PCI support for Quad cards

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Date:	Tue, 17 Apr 2007 13:24:53 +0530
From:	Mithlesh Thukral <mithlesh@...xen.com>
To:	Stephen Hemminger <shemminger@...ux-foundation.org>
Cc:	netdev@...r.kernel.org, amitkale@...xen.com, jeff@...zik.org,
	netxenproj@...syssoft.com, rob@...xen.com
Subject: Re: [PATCH 3/7] NetXen: Multi PCI support for Quad cards

On Monday 16 April 2007 23:19, Stephen Hemminger wrote:
> On Fri, 13 Apr 2007 08:39:31 -0700
>
> Linsys Contractor Mithlesh Thukral <mithlesh@...xen.com> wrote:
> > NetXen: Fix the multi PCI function for cards with more than 2 ports.
> > This patch fixes the working of multi PCI capable driver on cards with
> > more than 2 ports by adding the addresses for their rings and sizes.
> >
> > Signed-off by: Mithlesh Thukral <mithlesh@...xen.com>
> >
> > ---
> >
> >  drivers/net/netxen/netxen_nic_hw.c       |  119 +++++++++++++++++++--
> >  drivers/net/netxen/netxen_nic_init.c     |    4
> >  drivers/net/netxen/netxen_nic_main.c     |   61 +++++-----
> >  drivers/net/netxen/netxen_nic_phan_reg.h |    6 -
> >  4 files changed, 146 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/net/netxen/netxen_nic_hw.c
> > b/drivers/net/netxen/netxen_nic_hw.c index a066208..274a261 100644
> > --- a/drivers/net/netxen/netxen_nic_hw.c
> > +++ b/drivers/net/netxen/netxen_nic_hw.c
> > @@ -140,8 +140,105 @@ struct netxen_recv_crb recv_crb_register
> >  	 NETXEN_NIC_REG(0x180),
> >  	 /* crb_status_ring_size */
> >  	 NETXEN_NIC_REG(0x184),
> > -
> >  	 },
> > +	/*
> > +	 * Instance 3,
> > +	 */
> > +	{
> > +	  {
> > +	    {
> > +	    /* crb_rcv_producer_offset: */
> > +	    NETXEN_NIC_REG(0x1d8),
> > +	    /* crb_rcv_consumer_offset: */
> > +	    NETXEN_NIC_REG(0x1dc),
> > +	    /* crb_gloablrcv_ring: */
> > +	    NETXEN_NIC_REG(0x1f0),
> > +	    /* crb_rcv_ring_size */
> > +	    NETXEN_NIC_REG(0x1f4),
> > +	    },
> > +	    /* Jumbo frames */
> > +	    {
> > +	    /* crb_rcv_producer_offset: */
> > +	    NETXEN_NIC_REG(0x1f8),
> > +	    /* crb_rcv_consumer_offset: */
> > +	    NETXEN_NIC_REG(0x1fc),
> > +	    /* crb_gloablrcv_ring: */
> > +	    NETXEN_NIC_REG(0x200),
> > +	    /* crb_rcv_ring_size */
> > +	    NETXEN_NIC_REG(0x204),
> > +	    },
> > +	    /* LRO */
> > +	    {
> > +	    /* crb_rcv_producer_offset: */
> > +	    NETXEN_NIC_REG(0x208),
> > +	    /* crb_rcv_consumer_offset: */
> > +	    NETXEN_NIC_REG(0x20c),
> > +	    /* crb_gloablrcv_ring: */
> > +	    NETXEN_NIC_REG(0x210),
> > +	    /* crb_rcv_ring_size */
> > +	    NETXEN_NIC_REG(0x214),
> > +	    }
> > +	  },
> > +	  /* crb_rcvstatus_ring: */
> > +	  NETXEN_NIC_REG(0x218),
> > +	  /* crb_rcv_status_producer: */
> > +	  NETXEN_NIC_REG(0x21c),
> > +	  /* crb_rcv_status_consumer: */
> > +	  NETXEN_NIC_REG(0x220),
> > +	  /* crb_rcvpeg_state: */
> > +	  NETXEN_NIC_REG(0x224),
> > +	  /* crb_status_ring_size */
> > +	  NETXEN_NIC_REG(0x228),
> > +	},
> > +	/*
> > +	 * Instance 4,
> > +	 */
> > +	{
> > +	  {
> > +	    {
> > +	    /* crb_rcv_producer_offset: */
> > +	    NETXEN_NIC_REG(0x22c),
> > +	    /* crb_rcv_consumer_offset: */
> > +	    NETXEN_NIC_REG(0x230),
> > +	    /* crb_gloablrcv_ring: */
> > +	    NETXEN_NIC_REG(0x234),
> > +	    /* crb_rcv_ring_size */
> > +	    NETXEN_NIC_REG(0x238),
> > +	    },
> > +	    /* Jumbo frames */
> > +	    {
> > +	    /* crb_rcv_producer_offset: */
> > +	    NETXEN_NIC_REG(0x23c),
> > +	    /* crb_rcv_consumer_offset: */
> > +	    NETXEN_NIC_REG(0x240),
> > +	    /* crb_gloablrcv_ring: */
> > +	    NETXEN_NIC_REG(0x244),
> > +	    /* crb_rcv_ring_size */
> > +	    NETXEN_NIC_REG(0x248),
> > +	    },
> > +	    /* LRO */
> > +	    {
> > +	    /* crb_rcv_producer_offset: */
> > +	    NETXEN_NIC_REG(0x24c),
> > +	    /* crb_rcv_consumer_offset: */
> > +	    NETXEN_NIC_REG(0x250),
> > +	    /* crb_gloablrcv_ring: */
> > +	    NETXEN_NIC_REG(0x254),
> > +	    /* crb_rcv_ring_size */
> > +	    NETXEN_NIC_REG(0x258),
> > +	    }
> > +	  },
> > +	  /* crb_rcvstatus_ring: */
> > +	  NETXEN_NIC_REG(0x25c),
> > +	  /* crb_rcv_status_producer: */
> > +	  NETXEN_NIC_REG(0x260),
> > +	  /* crb_rcv_status_consumer: */
> > +	  NETXEN_NIC_REG(0x264),
> > +	  /* crb_rcvpeg_state: */
> > +	  NETXEN_NIC_REG(0x268),
> > +	  /* crb_status_ring_size */
> > +	  NETXEN_NIC_REG(0x26c),
> > +	},
> >  };
> >
> >  u64 ctx_addr_sig_regs[][3] = {
> > @@ -294,6 +391,7 @@ int netxen_nic_hw_resources(struct netxe
> >  	u32 card_cmdring = 0;
> >  	struct netxen_recv_context *recv_ctx;
> >  	struct netxen_rcv_desc_ctx *rcv_desc;
> > +	int func_id = adapter->portnum;
> >
> >  	DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
> >  		PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
> > @@ -341,7 +439,7 @@ int netxen_nic_hw_resources(struct netxe
> >  			    &adapter->ctx_desc_pdev);
> >
> >  	printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
> > -	       (unsigned long long) adapter->ctx_desc_phys_addr);
> > +	       (u64) adapter->ctx_desc_phys_addr);
>
> This will give a warning on 64 bit platforms because format doesn't match
> width. You need to cast to (unsigned long long).
Thanks for pointing this out.
I will fix this in a repost of the patch set.

Regards,
Mithlesh Thukral
-
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