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Date: Thu, 01 Nov 2007 11:54:24 +0200
From: "Eliezer Tamir" <eliezert@...adcom.com>
To: davem@...emloft.net
Subject: Re: [PATCH][BNX2X] added register coments - bnx2x_reg.h
posting individual files for comments.
---
/* bnx2x_reg.h: Broadcom Everest network driver.
*
* Copyright (c) 2007 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* The registers description starts with the regsister Access type followed
* by size in bits. For example [RW 32]. The access types are:
* R - Read only
* RC - Clear on read
* RW - Read/Write
* ST - Statistics register (clear on read)
* W - Write only
* WB - Wide bus register - the size is over 32 bits and it should be
* read/write in consecutive 32 bits accesses
* WR - Write Clear (write 1 to clear the bit)
*
*/
/* [R 19] Interrupt register #0 read */
#define BRB1_REG_BRB1_INT_STS 0x6011c
/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
/* [RW 23] LL RAM data. */
#define BRB1_REG_LL_RAM 0x61000
/* [R 24] The number of full blocks. */
#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
/* [ST 32] The number of cycles that the write_full signal towards MAC #0
was asserted. */
#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
asserted. */
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
/* [RW 10] Write client 0: De-assert pause threshold. */
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
/* [RW 10] Write client 0: Assert pause threshold. */
#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
/* [RW 1] Reset the design by software. */
#define BRB1_REG_SOFT_RESET 0x600dc
/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
#define CCM_REG_CAM_OCCUP 0xd0188
/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_CFC_IFEN 0xd003c
/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
disregarded; valid is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_CQM_IFEN 0xd000c
/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
Otherwise 0 is inserted. */
#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
/* [R 11] Interrupt register #0 read */
#define CCM_REG_CCM_INT_STS 0xd01d8
/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
Is used to determine the number of the AG context REG-pairs written back;
when the input message Reg1WbFlg isn't set. */
#define CCM_REG_CCM_REG0_SZ 0xd00c4
/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
disregarded; valid is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_STORM0_IFEN 0xd0004
/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
disregarded; valid is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_STORM1_IFEN 0xd0008
/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
disregarded; valid output is deasserted; all other signals are treated as
usual; if 1 - normal activity. */
#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
are disregarded; all other signals are treated as usual; if 1 - normal
activity. */
#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
disregarded; valid output is deasserted; all other signals are treated as
usual; if 1 - normal activity. */
#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
input is disregarded; all other signals are treated as usual; if 1 -
normal activity. */
#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
the initial credit value; read returns the current value of the credit
counter. Must be initialized to 1 at start-up. */
#define CCM_REG_CFC_INIT_CRD 0xd0204
/* [RW 2] Auxillary counter flag Q number 1. */
#define CCM_REG_CNT_AUX1_Q 0xd00c8
/* [RW 2] Auxillary counter flag Q number 2. */
#define CCM_REG_CNT_AUX2_Q 0xd00cc
/* [RW 28] The CM header value for QM request (primary). */
#define CCM_REG_CQM_CCM_HDR_P 0xd008c
/* [RW 28] The CM header value for QM request (secondary). */
#define CCM_REG_CQM_CCM_HDR_S 0xd0090
/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CQM_CCM_IFEN 0xd0014
/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
the initial credit value; read returns the current value of the credit
counter. Must be initialized to 32 at start-up. */
#define CCM_REG_CQM_INIT_CRD 0xd020c
/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_CQM_P_WEIGHT 0xd00b8
/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CSDM_IFEN 0xd0018
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the SDM interface is detected. */
#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
/* [RW 28] The CM header for QM formatting in case of an error in the QM
inputs. */
#define CCM_REG_ERR_CCM_HDR 0xd0094
/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
#define CCM_REG_ERR_EVNT_ID 0xd0098
/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 64 at start-up. */
#define CCM_REG_FIC0_INIT_CRD 0xd0210
/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 64 at start-up. */
#define CCM_REG_FIC1_INIT_CRD 0xd0214
/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
- strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
~ccm_registers_gr_ld0_pr.gr_ld0_pr and
~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
#define CCM_REG_GR_ARB_TYPE 0xd015c
/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
highest priority is 3. It is supposed; that the Store channel priority is
the compliment to 4 of the rest priorities - Aggregation channel; Load
(FIC0) channel and Load (FIC1). */
#define CCM_REG_GR_LD0_PR 0xd0164
/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
highest priority is 3. It is supposed; that the Store channel priority is
the compliment to 4 of the rest priorities - Aggregation channel; Load
(FIC0) channel and Load (FIC1). */
#define CCM_REG_GR_LD1_PR 0xd0168
/* [RW 2] General flags index. */
#define CCM_REG_INV_DONE_Q 0xd0108
/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
context and sent to STORM; for a specific connection type. The double
REG-pairs are used in order to align to STORM context row size of 128
bits. The offset of these data in the STORM context is always 0. Index
_(0..15) stands for the connection type (one of 16). */
#define CCM_REG_N_SM_CTX_LD_0 0xd004c
#define CCM_REG_N_SM_CTX_LD_1 0xd0050
#define CCM_REG_N_SM_CTX_LD_10 0xd0074
#define CCM_REG_N_SM_CTX_LD_11 0xd0078
#define CCM_REG_N_SM_CTX_LD_12 0xd007c
#define CCM_REG_N_SM_CTX_LD_13 0xd0080
#define CCM_REG_N_SM_CTX_LD_14 0xd0084
#define CCM_REG_N_SM_CTX_LD_15 0xd0088
#define CCM_REG_N_SM_CTX_LD_2 0xd0054
#define CCM_REG_N_SM_CTX_LD_3 0xd0058
#define CCM_REG_N_SM_CTX_LD_4 0xd005c
/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_PBF_IFEN 0xd0028
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the pbf interface is detected. */
#define CCM_REG_PBF_LENGTH_MIS 0xd0180
/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_PBF_WEIGHT 0xd00ac
/* [RW 6] The physical queue number of queue number 1 per port index. */
#define CCM_REG_PHYS_QNUM1_0 0xd0134
#define CCM_REG_PHYS_QNUM1_1 0xd0138
/* [RW 6] The physical queue number of queue number 2 per port index. */
#define CCM_REG_PHYS_QNUM2_0 0xd013c
#define CCM_REG_PHYS_QNUM2_1 0xd0140
/* [RW 6] The physical queue number of queue number 3 per port index. */
#define CCM_REG_PHYS_QNUM3_0 0xd0144
/* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port
index 0. */
#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
/* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port
index 0. */
#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
/* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port
index 0. */
#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
/* [RW 6] The physical queue number of queue number 0 with QOS equal 3 port
index 0. */
#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_STORM_CCM_IFEN 0xd0010
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the STORM interface is detected. */
#define CCM_REG_STORM_LENGTH_MIS 0xd016c
/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_TSEM_IFEN 0xd001c
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the tsem interface is detected. */
#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_TSEM_WEIGHT 0xd00a0
/* [RW 1] Input usem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_USEM_IFEN 0xd0024
/* [RC 1] Set when message length mismatch (relative to last indication) at
the usem interface is detected. */
#define CCM_REG_USEM_LENGTH_MIS 0xd017c
/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_USEM_WEIGHT 0xd00a8
/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_XSEM_IFEN 0xd0020
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the xsem interface is detected. */
#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_XSEM_WEIGHT 0xd00a4
/* [RW 19] Indirect access to the descriptor table of the XX protection
mechanism. The fields are: [5:0] - message length; [12:6] - message
pointer; 18:13] - next pointer. */
#define CCM_REG_XX_DESCR_TABLE 0xd0300
/* [R 7] Used to read the value of XX protection Free counter. */
#define CCM_REG_XX_FREE 0xd0184
/* [RW 6] Initial value for the credit counter; responsible for fulfilling
of the Input Stage XX protection buffer by the XX protection pending
messages. Max credit available - 127. Write writes the initial credit
value; read returns the current value of the credit counter. Must be
initialized to maximum XX protected message size - 2 at start-up. */
#define CCM_REG_XX_INIT_CRD 0xd0220
/* [RW 7] The maximum number of pending messages; which may be stored in XX
protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
At write comprises the start value of the ~ccm_registers_xx_free.xx_free
counter. */
#define CCM_REG_XX_MSG_NUM 0xd0224
/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
header pointer. */
#define CCM_REG_XX_TABLE 0xd0280
#define CDU_REG_CDU_CHK_MASK0 0x101000
#define CDU_REG_CDU_CHK_MASK1 0x101004
#define CDU_REG_CDU_CONTROL0 0x101008
#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
/* [R 7] Interrupt register #0 read */
#define CDU_REG_CDU_INT_STS 0x101030
/* [RC 32] logging of error data in case of a CDU load error:
{expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
ype_error; ctual_active; ctual_compressed_context}; */
#define CDU_REG_ERROR_DATA 0x101014
/* [WB 216] L1TT ram access. each entry has the following format :
{mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
#define CDU_REG_L1TT 0x101800
/* [WB 24] MATT ram access. each entry has the following
format:{RegionLength[11:0]; egionOffset[11:0]} */
#define CDU_REG_MATT 0x101100
/* [R 1] indication the initializing the activity counter by the hardware
was done. */
#define CFC_REG_AC_INIT_DONE 0x104078
/* [RW 13] activity counter ram access */
#define CFC_REG_ACTIVITY_COUNTER 0x104400
#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
/* [R 1] indication the initializing the cams by the hardware was done. */
#define CFC_REG_CAM_INIT_DONE 0x10407c
/* [R 2] Interrupt register #0 read */
#define CFC_REG_CFC_INT_STS 0x1040fc
/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
#define CFC_REG_CID_CAM 0x104800
#define CFC_REG_CONTROL0 0x104028
#define CFC_REG_DEBUG0 0x104050
/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
vector) whether the cfc should be disabled upon it */
#define CFC_REG_DISABLE_ON_ERROR 0x104044
/* [RC 14] CFC error vector. when the CFC detects an internal error it will
set one of these bits. the bit description can be found in CFC
specifications */
#define CFC_REG_ERROR_VECTOR 0x10403c
#define CFC_REG_INIT_REG 0x10404c
/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
field allows changing the priorities of the weighted-round-robin arbiter
which selects which CFC load client should be served next */
#define CFC_REG_LCREQ_WEIGHTS 0x104084
/* [R 1] indication the initializing the link list by the hardware was done. */
#define CFC_REG_LL_INIT_DONE 0x104074
/* [R 9] Number of allocated LCIDs which are at empty state */
#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
/* [R 9] Number of Arriving LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
/* [R 9] Number of Inside LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_INSIDE 0x104008
/* [R 9] Number of Leaving LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
/* [RW 8] The event id for aggregated interrupt 0 */
#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
/* [RW 16] The maximum value of the competion counter #0 */
#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
/* [RW 16] The maximum value of the competion counter #1 */
#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
/* [RW 16] The maximum value of the competion counter #2 */
#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
/* [RW 16] The maximum value of the competion counter #3 */
#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
/* [RW 13] The start address in the internal RAM for the completion
counters. */
#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
#define CSDM_REG_ENABLE_IN1 0xc2238
#define CSDM_REG_ENABLE_IN2 0xc223c
#define CSDM_REG_ENABLE_OUT1 0xc2240
#define C
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