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Date: Tue, 09 Dec 2008 19:50:49 +0530
From: Sathya Perla <sathyap@...verengines.com>
To: netdev <netdev@...r.kernel.org>
Cc: Jeff Garzik <jgarzik@...ox.com>, subbu <subbus@...verengines.com>
Subject: [PATCH 08/11] benet: hardware host interface header files
Signed-off-by: Sathya Perla <sathyap@...verengines.com>
---
drivers/net/benet/cev.h | 243 ++++++++++++++++++++++++++++++++++++++
drivers/net/benet/doorbells.h | 179 ++++++++++++++++++++++++++++
drivers/net/benet/fwcmd_common.h | 222 ++++++++++++++++++++++++++++++++++
drivers/net/benet/host_struct.h | 182 ++++++++++++++++++++++++++++
drivers/net/benet/post_codes.h | 111 +++++++++++++++++
5 files changed, 937 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/benet/cev.h
create mode 100644 drivers/net/benet/doorbells.h
create mode 100644 drivers/net/benet/fwcmd_common.h
create mode 100644 drivers/net/benet/host_struct.h
create mode 100644 drivers/net/benet/post_codes.h
diff --git a/drivers/net/benet/cev.h b/drivers/net/benet/cev.h
new file mode 100644
index 0000000..3099692
--- /dev/null
+++ b/drivers/net/benet/cev.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __cev_amap_h__
+#define __cev_amap_h__
+#include "ep.h"
+
+/*
+ * Host Interrupt Status Register 0. The first of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ0 through EQ31.
+ */
+struct BE_CEV_ISR0_CSR_AMAP {
+ u8 interrupt0; /* DWORD 0 */
+ u8 interrupt1; /* DWORD 0 */
+ u8 interrupt2; /* DWORD 0 */
+ u8 interrupt3; /* DWORD 0 */
+ u8 interrupt4; /* DWORD 0 */
+ u8 interrupt5; /* DWORD 0 */
+ u8 interrupt6; /* DWORD 0 */
+ u8 interrupt7; /* DWORD 0 */
+ u8 interrupt8; /* DWORD 0 */
+ u8 interrupt9; /* DWORD 0 */
+ u8 interrupt10; /* DWORD 0 */
+ u8 interrupt11; /* DWORD 0 */
+ u8 interrupt12; /* DWORD 0 */
+ u8 interrupt13; /* DWORD 0 */
+ u8 interrupt14; /* DWORD 0 */
+ u8 interrupt15; /* DWORD 0 */
+ u8 interrupt16; /* DWORD 0 */
+ u8 interrupt17; /* DWORD 0 */
+ u8 interrupt18; /* DWORD 0 */
+ u8 interrupt19; /* DWORD 0 */
+ u8 interrupt20; /* DWORD 0 */
+ u8 interrupt21; /* DWORD 0 */
+ u8 interrupt22; /* DWORD 0 */
+ u8 interrupt23; /* DWORD 0 */
+ u8 interrupt24; /* DWORD 0 */
+ u8 interrupt25; /* DWORD 0 */
+ u8 interrupt26; /* DWORD 0 */
+ u8 interrupt27; /* DWORD 0 */
+ u8 interrupt28; /* DWORD 0 */
+ u8 interrupt29; /* DWORD 0 */
+ u8 interrupt30; /* DWORD 0 */
+ u8 interrupt31; /* DWORD 0 */
+} __packed;
+struct CEV_ISR0_CSR_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Host Interrupt Status Register 1. The second of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ32 through EQ63.
+ */
+struct BE_CEV_ISR1_CSR_AMAP {
+ u8 interrupt32; /* DWORD 0 */
+ u8 interrupt33; /* DWORD 0 */
+ u8 interrupt34; /* DWORD 0 */
+ u8 interrupt35; /* DWORD 0 */
+ u8 interrupt36; /* DWORD 0 */
+ u8 interrupt37; /* DWORD 0 */
+ u8 interrupt38; /* DWORD 0 */
+ u8 interrupt39; /* DWORD 0 */
+ u8 interrupt40; /* DWORD 0 */
+ u8 interrupt41; /* DWORD 0 */
+ u8 interrupt42; /* DWORD 0 */
+ u8 interrupt43; /* DWORD 0 */
+ u8 interrupt44; /* DWORD 0 */
+ u8 interrupt45; /* DWORD 0 */
+ u8 interrupt46; /* DWORD 0 */
+ u8 interrupt47; /* DWORD 0 */
+ u8 interrupt48; /* DWORD 0 */
+ u8 interrupt49; /* DWORD 0 */
+ u8 interrupt50; /* DWORD 0 */
+ u8 interrupt51; /* DWORD 0 */
+ u8 interrupt52; /* DWORD 0 */
+ u8 interrupt53; /* DWORD 0 */
+ u8 interrupt54; /* DWORD 0 */
+ u8 interrupt55; /* DWORD 0 */
+ u8 interrupt56; /* DWORD 0 */
+ u8 interrupt57; /* DWORD 0 */
+ u8 interrupt58; /* DWORD 0 */
+ u8 interrupt59; /* DWORD 0 */
+ u8 interrupt60; /* DWORD 0 */
+ u8 interrupt61; /* DWORD 0 */
+ u8 interrupt62; /* DWORD 0 */
+ u8 interrupt63; /* DWORD 0 */
+} __packed;
+struct CEV_ISR1_CSR_AMAP {
+ u32 dw[1];
+};
+/*
+ * Host Interrupt Status Register 2. The third of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ64 through EQ95.
+ */
+struct BE_CEV_ISR2_CSR_AMAP {
+ u8 interrupt64; /* DWORD 0 */
+ u8 interrupt65; /* DWORD 0 */
+ u8 interrupt66; /* DWORD 0 */
+ u8 interrupt67; /* DWORD 0 */
+ u8 interrupt68; /* DWORD 0 */
+ u8 interrupt69; /* DWORD 0 */
+ u8 interrupt70; /* DWORD 0 */
+ u8 interrupt71; /* DWORD 0 */
+ u8 interrupt72; /* DWORD 0 */
+ u8 interrupt73; /* DWORD 0 */
+ u8 interrupt74; /* DWORD 0 */
+ u8 interrupt75; /* DWORD 0 */
+ u8 interrupt76; /* DWORD 0 */
+ u8 interrupt77; /* DWORD 0 */
+ u8 interrupt78; /* DWORD 0 */
+ u8 interrupt79; /* DWORD 0 */
+ u8 interrupt80; /* DWORD 0 */
+ u8 interrupt81; /* DWORD 0 */
+ u8 interrupt82; /* DWORD 0 */
+ u8 interrupt83; /* DWORD 0 */
+ u8 interrupt84; /* DWORD 0 */
+ u8 interrupt85; /* DWORD 0 */
+ u8 interrupt86; /* DWORD 0 */
+ u8 interrupt87; /* DWORD 0 */
+ u8 interrupt88; /* DWORD 0 */
+ u8 interrupt89; /* DWORD 0 */
+ u8 interrupt90; /* DWORD 0 */
+ u8 interrupt91; /* DWORD 0 */
+ u8 interrupt92; /* DWORD 0 */
+ u8 interrupt93; /* DWORD 0 */
+ u8 interrupt94; /* DWORD 0 */
+ u8 interrupt95; /* DWORD 0 */
+} __packed;
+struct CEV_ISR2_CSR_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Host Interrupt Status Register 3. The fourth of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ96 through EQ127.
+ */
+struct BE_CEV_ISR3_CSR_AMAP {
+ u8 interrupt96; /* DWORD 0 */
+ u8 interrupt97; /* DWORD 0 */
+ u8 interrupt98; /* DWORD 0 */
+ u8 interrupt99; /* DWORD 0 */
+ u8 interrupt100; /* DWORD 0 */
+ u8 interrupt101; /* DWORD 0 */
+ u8 interrupt102; /* DWORD 0 */
+ u8 interrupt103; /* DWORD 0 */
+ u8 interrupt104; /* DWORD 0 */
+ u8 interrupt105; /* DWORD 0 */
+ u8 interrupt106; /* DWORD 0 */
+ u8 interrupt107; /* DWORD 0 */
+ u8 interrupt108; /* DWORD 0 */
+ u8 interrupt109; /* DWORD 0 */
+ u8 interrupt110; /* DWORD 0 */
+ u8 interrupt111; /* DWORD 0 */
+ u8 interrupt112; /* DWORD 0 */
+ u8 interrupt113; /* DWORD 0 */
+ u8 interrupt114; /* DWORD 0 */
+ u8 interrupt115; /* DWORD 0 */
+ u8 interrupt116; /* DWORD 0 */
+ u8 interrupt117; /* DWORD 0 */
+ u8 interrupt118; /* DWORD 0 */
+ u8 interrupt119; /* DWORD 0 */
+ u8 interrupt120; /* DWORD 0 */
+ u8 interrupt121; /* DWORD 0 */
+ u8 interrupt122; /* DWORD 0 */
+ u8 interrupt123; /* DWORD 0 */
+ u8 interrupt124; /* DWORD 0 */
+ u8 interrupt125; /* DWORD 0 */
+ u8 interrupt126; /* DWORD 0 */
+ u8 interrupt127; /* DWORD 0 */
+} __packed;
+struct CEV_ISR3_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Completions and Events block Registers. */
+struct BE_CEV_CSRMAP_AMAP {
+ u8 rsvd0[32]; /* DWORD 0 */
+ u8 rsvd1[32]; /* DWORD 1 */
+ u8 rsvd2[32]; /* DWORD 2 */
+ u8 rsvd3[32]; /* DWORD 3 */
+ struct BE_CEV_ISR0_CSR_AMAP isr0;
+ struct BE_CEV_ISR1_CSR_AMAP isr1;
+ struct BE_CEV_ISR2_CSR_AMAP isr2;
+ struct BE_CEV_ISR3_CSR_AMAP isr3;
+ u8 rsvd4[32]; /* DWORD 8 */
+ u8 rsvd5[32]; /* DWORD 9 */
+ u8 rsvd6[32]; /* DWORD 10 */
+ u8 rsvd7[32]; /* DWORD 11 */
+ u8 rsvd8[32]; /* DWORD 12 */
+ u8 rsvd9[32]; /* DWORD 13 */
+ u8 rsvd10[32]; /* DWORD 14 */
+ u8 rsvd11[32]; /* DWORD 15 */
+ u8 rsvd12[32]; /* DWORD 16 */
+ u8 rsvd13[32]; /* DWORD 17 */
+ u8 rsvd14[32]; /* DWORD 18 */
+ u8 rsvd15[32]; /* DWORD 19 */
+ u8 rsvd16[32]; /* DWORD 20 */
+ u8 rsvd17[32]; /* DWORD 21 */
+ u8 rsvd18[32]; /* DWORD 22 */
+ u8 rsvd19[32]; /* DWORD 23 */
+ u8 rsvd20[32]; /* DWORD 24 */
+ u8 rsvd21[32]; /* DWORD 25 */
+ u8 rsvd22[32]; /* DWORD 26 */
+ u8 rsvd23[32]; /* DWORD 27 */
+ u8 rsvd24[32]; /* DWORD 28 */
+ u8 rsvd25[32]; /* DWORD 29 */
+ u8 rsvd26[32]; /* DWORD 30 */
+ u8 rsvd27[32]; /* DWORD 31 */
+ u8 rsvd28[32]; /* DWORD 32 */
+ u8 rsvd29[32]; /* DWORD 33 */
+ u8 rsvd30[192]; /* DWORD 34 */
+ u8 rsvd31[192]; /* DWORD 40 */
+ u8 rsvd32[160]; /* DWORD 46 */
+ u8 rsvd33[160]; /* DWORD 51 */
+ u8 rsvd34[160]; /* DWORD 56 */
+ u8 rsvd35[96]; /* DWORD 61 */
+ u8 rsvd36[192][32]; /* DWORD 64 */
+} __packed;
+struct CEV_CSRMAP_AMAP {
+ u32 dw[256];
+};
+
+#endif /* __cev_amap_h__ */
diff --git a/drivers/net/benet/doorbells.h b/drivers/net/benet/doorbells.h
new file mode 100644
index 0000000..550cc4d
--- /dev/null
+++ b/drivers/net/benet/doorbells.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __doorbells_amap_h__
+#define __doorbells_amap_h__
+
+/* The TX/RDMA send queue doorbell. */
+struct BE_SQ_DB_AMAP {
+ u8 cid[11]; /* DWORD 0 */
+ u8 rsvd0[5]; /* DWORD 0 */
+ u8 numPosted[14]; /* DWORD 0 */
+ u8 rsvd1[2]; /* DWORD 0 */
+} __packed;
+struct SQ_DB_AMAP {
+ u32 dw[1];
+};
+
+/* The receive queue doorbell. */
+struct BE_RQ_DB_AMAP {
+ u8 rq[10]; /* DWORD 0 */
+ u8 rsvd0[13]; /* DWORD 0 */
+ u8 Invalidate; /* DWORD 0 */
+ u8 numPosted[8]; /* DWORD 0 */
+} __packed;
+struct RQ_DB_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * The CQ/EQ doorbell. Software MUST set reserved fields in this
+ * descriptor to zero, otherwise (CEV) hardware will not execute the
+ * doorbell (flagging a bad_db_qid error instead).
+ */
+struct BE_CQ_DB_AMAP {
+ u8 qid[10]; /* DWORD 0 */
+ u8 rsvd0[4]; /* DWORD 0 */
+ u8 rearm; /* DWORD 0 */
+ u8 event; /* DWORD 0 */
+ u8 num_popped[13]; /* DWORD 0 */
+ u8 rsvd1[3]; /* DWORD 0 */
+} __packed;
+struct CQ_DB_AMAP {
+ u32 dw[1];
+};
+
+struct BE_TPM_RQ_DB_AMAP {
+ u8 qid[10]; /* DWORD 0 */
+ u8 rsvd0[6]; /* DWORD 0 */
+ u8 numPosted[11]; /* DWORD 0 */
+ u8 mss_cnt[5]; /* DWORD 0 */
+} __packed;
+struct TPM_RQ_DB_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Post WRB Queue Doorbell Register used by the host Storage stack
+ * to notify the controller of a posted Work Request Block
+ */
+struct BE_WRB_POST_DB_AMAP {
+ u8 wrb_cid[10]; /* DWORD 0 */
+ u8 rsvd0[6]; /* DWORD 0 */
+ u8 wrb_index[8]; /* DWORD 0 */
+ u8 numberPosted[8]; /* DWORD 0 */
+} __packed;
+struct WRB_POST_DB_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Update Default PDU Queue Doorbell Register used to communicate
+ * to the controller that the driver has stopped processing the queue
+ * and where in the queue it stopped, this is
+ * a CQ Entry Type. Used by storage driver.
+ */
+struct BE_DEFAULT_PDU_DB_AMAP {
+ u8 qid[10]; /* DWORD 0 */
+ u8 rsvd0[4]; /* DWORD 0 */
+ u8 rearm; /* DWORD 0 */
+ u8 event; /* DWORD 0 */
+ u8 cqproc[14]; /* DWORD 0 */
+ u8 rsvd1[2]; /* DWORD 0 */
+} __packed;
+struct DEFAULT_PDU_DB_AMAP {
+ u32 dw[1];
+};
+
+/* Management Command and Controller default fragment ring */
+struct BE_MCC_DB_AMAP {
+ u8 rid[11]; /* DWORD 0 */
+ u8 rsvd0[5]; /* DWORD 0 */
+ u8 numPosted[14]; /* DWORD 0 */
+ u8 rsvd1[2]; /* DWORD 0 */
+} __packed;
+struct MCC_DB_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Used for bootstrapping the Host interface. This register is
+ * used for driver communication with the MPU when no MCC Rings exist.
+ * The software must write this register twice to post any MCC
+ * command. First, it writes the register with hi=1 and the upper bits of
+ * the physical address for the MCC_MAILBOX structure. Software must poll
+ * the ready bit until this is acknowledged. Then, sotware writes the
+ * register with hi=0 with the lower bits in the address. It must
+ * poll the ready bit until the MCC command is complete. Upon completion,
+ * the MCC_MAILBOX will contain a valid completion queue entry.
+ */
+struct BE_MPU_MAILBOX_DB_AMAP {
+ u8 ready; /* DWORD 0 */
+ u8 hi; /* DWORD 0 */
+ u8 address[30]; /* DWORD 0 */
+} __packed;
+struct MPU_MAILBOX_DB_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * This is the protection domain doorbell register map. Note that
+ * while this map shows doorbells for all Blade Engine supported
+ * protocols, not all of these may be valid in a given function or
+ * protection domain. It is the responsibility of the application
+ * accessing the doorbells to know which are valid. Each doorbell
+ * occupies 32 bytes of space, but unless otherwise specified,
+ * only the first 4 bytes should be written. There are 32 instances
+ * of these doorbells for the host and 31 virtual machines respectively.
+ * The host and VMs will only map the doorbell pages belonging to its
+ * protection domain. It will not be able to touch the doorbells for
+ * another VM. The doorbells are the only registers directly accessible
+ * by a virtual machine. Similarly, there are 511 additional
+ * doorbells for RDMA protection domains. PD 0 for RDMA shares
+ * the same physical protection domain doorbell page as ETH/iSCSI.
+ *
+ */
+struct BE_PROTECTION_DOMAIN_DBMAP_AMAP {
+ u8 rsvd0[512]; /* DWORD 0 */
+ struct BE_SQ_DB_AMAP rdma_sq_db;
+ u8 rsvd1[7][32]; /* DWORD 17 */
+ struct BE_WRB_POST_DB_AMAP iscsi_wrb_post_db;
+ u8 rsvd2[7][32]; /* DWORD 25 */
+ struct BE_SQ_DB_AMAP etx_sq_db;
+ u8 rsvd3[7][32]; /* DWORD 33 */
+ struct BE_RQ_DB_AMAP rdma_rq_db;
+ u8 rsvd4[7][32]; /* DWORD 41 */
+ struct BE_DEFAULT_PDU_DB_AMAP iscsi_default_pdu_db;
+ u8 rsvd5[7][32]; /* DWORD 49 */
+ struct BE_TPM_RQ_DB_AMAP tpm_rq_db;
+ u8 rsvd6[7][32]; /* DWORD 57 */
+ struct BE_RQ_DB_AMAP erx_rq_db;
+ u8 rsvd7[7][32]; /* DWORD 65 */
+ struct BE_CQ_DB_AMAP cq_db;
+ u8 rsvd8[7][32]; /* DWORD 73 */
+ struct BE_MCC_DB_AMAP mpu_mcc_db;
+ u8 rsvd9[7][32]; /* DWORD 81 */
+ struct BE_MPU_MAILBOX_DB_AMAP mcc_bootstrap_db;
+ u8 rsvd10[935][32]; /* DWORD 89 */
+} __packed;
+struct PROTECTION_DOMAIN_DBMAP_AMAP {
+ u32 dw[1024];
+};
+
+#endif /* __doorbells_amap_h__ */
diff --git a/drivers/net/benet/fwcmd_common.h b/drivers/net/benet/fwcmd_common.h
new file mode 100644
index 0000000..406e0d6
--- /dev/null
+++ b/drivers/net/benet/fwcmd_common.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __fwcmd_common_amap_h__
+#define __fwcmd_common_amap_h__
+#include "host_struct.h"
+
+/* --- PHY_LINK_DUPLEX_ENUM --- */
+#define PHY_LINK_DUPLEX_NONE (0)
+#define PHY_LINK_DUPLEX_HALF (1)
+#define PHY_LINK_DUPLEX_FULL (2)
+
+/* --- PHY_LINK_SPEED_ENUM --- */
+#define PHY_LINK_SPEED_ZERO (0) /* No link. */
+#define PHY_LINK_SPEED_10MBPS (1) /* 10 Mbps */
+#define PHY_LINK_SPEED_100MBPS (2) /* 100 Mbps */
+#define PHY_LINK_SPEED_1GBPS (3) /* 1 Gbps */
+#define PHY_LINK_SPEED_10GBPS (4) /* 10 Gbps */
+
+/* --- PHY_LINK_FAULT_ENUM --- */
+#define PHY_LINK_FAULT_NONE (0) /* No fault status
+ available or detected */
+#define PHY_LINK_FAULT_LOCAL (1) /* Local fault detected */
+#define PHY_LINK_FAULT_REMOTE (2) /* Remote fault detected */
+
+/* --- BE_ULP_MASK --- */
+#define BE_ULP0_MASK (1)
+#define BE_ULP1_MASK (2)
+#define BE_ULP2_MASK (4)
+
+/* --- NTWK_ACTIVE_PORT --- */
+#define NTWK_PORT_A (0) /* Port A is currently active */
+#define NTWK_PORT_B (1) /* Port B is currently active */
+#define NTWK_NO_ACTIVE_PORT (15) /* Both ports have lost link */
+
+/* --- NTWK_LINK_TYPE --- */
+#define NTWK_LINK_TYPE_PHYSICAL (0) /* link up/down event
+ applies to BladeEngine's
+ Physical Ports
+ */
+#define NTWK_LINK_TYPE_VIRTUAL (1) /* Virtual link up/down event
+ reported by BladeExchange.
+ This applies only when the
+ VLD feature is enabled
+ */
+
+/*
+ * --- FWCMD_MAC_TYPE_ENUM ---
+ * This enum defines the types of MAC addresses in the RXF MAC Address Table.
+ */
+#define MAC_ADDRESS_TYPE_STORAGE (0) /* Storage MAC Address */
+#define MAC_ADDRESS_TYPE_NETWORK (1) /* Network MAC Address */
+#define MAC_ADDRESS_TYPE_PD (2) /* Protection Domain MAC Addr */
+#define MAC_ADDRESS_TYPE_MANAGEMENT (3) /* Managment MAC Address */
+
+
+/* --- FWCMD_RING_TYPE_ENUM --- */
+#define FWCMD_RING_TYPE_ETH_RX (1) /* Ring created with */
+ /* FWCMD_COMMON_ETH_RX_CREATE. */
+#define FWCMD_RING_TYPE_ETH_TX (2) /* Ring created with */
+ /* FWCMD_COMMON_ETH_TX_CREATE. */
+#define FWCMD_RING_TYPE_ISCSI_WRBQ (3) /* Ring created with */
+ /* FWCMD_COMMON_ISCSI_WRBQ_CREATE. */
+#define FWCMD_RING_TYPE_ISCSI_DEFQ (4) /* Ring created with */
+ /* FWCMD_COMMON_ISCSI_DEFQ_CREATE. */
+#define FWCMD_RING_TYPE_TPM_WRBQ (5) /* Ring created with */
+ /* FWCMD_COMMON_TPM_WRBQ_CREATE. */
+#define FWCMD_RING_TYPE_TPM_DEFQ (6) /* Ring created with */
+ /* FWCMD_COMMONTPM_TDEFQ_CREATE. */
+#define FWCMD_RING_TYPE_TPM_RQ (7) /* Ring created with */
+ /* FWCMD_COMMON_TPM_RQ_CREATE. */
+#define FWCMD_RING_TYPE_MCC (8) /* Ring created with */
+ /* FWCMD_COMMON_MCC_CREATE. */
+#define FWCMD_RING_TYPE_CQ (9) /* Ring created with */
+ /* FWCMD_COMMON_CQ_CREATE. */
+#define FWCMD_RING_TYPE_EQ (10) /* Ring created with */
+ /* FWCMD_COMMON_EQ_CREATE. */
+#define FWCMD_RING_TYPE_QP (11) /* Ring created with */
+ /* FWCMD_RDMA_QP_CREATE. */
+
+
+/* --- ETH_TX_RING_TYPE_ENUM --- */
+#define ETH_TX_RING_TYPE_FORWARDING (1) /* Ethernet ring for
+ forwarding packets */
+#define ETH_TX_RING_TYPE_STANDARD (2) /* Ethernet ring for sending
+ network packets. */
+#define ETH_TX_RING_TYPE_BOUND (3) /* Ethernet ring bound to the
+ port specified in the command
+ header.port_number field.
+ Rings of this type are
+ NOT subject to the
+ failover logic implemented
+ in the BladeEngine.
+ */
+
+/* --- FWCMD_COMMON_QOS_TYPE_ENUM --- */
+#define QOS_BITS_NIC (1) /* max_bits_per_second_NIC */
+ /* field is valid. */
+#define QOS_PKTS_NIC (2) /* max_packets_per_second_NIC */
+ /* field is valid. */
+#define QOS_IOPS_ISCSI (4) /* max_ios_per_second_iSCSI */
+ /*field is valid. */
+#define QOS_VLAN_TAG (8) /* domain_VLAN_tag field
+ is valid. */
+#define QOS_FABRIC_ID (16) /* fabric_domain_ID field
+ is valid. */
+#define QOS_OEM_PARAMS (32) /* qos_params_oem field
+ is valid. */
+#define QOS_TPUT_ISCSI (64) /* max_bytes_per_second_iSCSI
+ field is valid. */
+
+
+/*
+ * --- FAILOVER_CONFIG_ENUM ---
+ * Failover configuration setting used in FWCMD_COMMON_FORCE_FAILOVER
+ */
+#define FAILOVER_CONFIG_NO_CHANGE (0) /* No change to automatic */
+ /* port failover setting. */
+#define FAILOVER_CONFIG_ON (1) /* Automatic port failover
+ on link down is enabled. */
+#define FAILOVER_CONFIG_OFF (2) /* Automatic port failover
+ on link down is disabled. */
+
+/*
+ * --- FAILOVER_PORT_ENUM ---
+ * Failover port setting used in FWCMD_COMMON_FORCE_FAILOVER
+ */
+#define FAILOVER_PORT_A (0) /* Selects port A. */
+#define FAILOVER_PORT_B (1) /* Selects port B. */
+#define FAILOVER_PORT_NONE (15) /* No port change requested. */
+
+
+/*
+ * --- MGMT_FLASHROM_OPCODE ---
+ * Flash ROM operation code
+ */
+#define MGMT_FLASHROM_OPCODE_FLASH (1) /* Commit downloaded data
+ to Flash ROM */
+#define MGMT_FLASHROM_OPCODE_SAVE (2) /* Save downloaded data to
+ ARM's DDR - do not flash */
+#define MGMT_FLASHROM_OPCODE_CLEAR (3) /* Erase specified component
+ from FlashROM */
+#define MGMT_FLASHROM_OPCODE_REPORT (4) /* Read specified component
+ from Flash ROM */
+#define MGMT_FLASHROM_OPCODE_IMAGE_INFO (5) /* Returns size of a
+ component */
+
+/*
+ * --- MGMT_FLASHROM_OPTYPE ---
+ * Flash ROM operation type
+ */
+#define MGMT_FLASHROM_OPTYPE_CODE_FIRMWARE (0) /* Includes ARM firmware,
+ IPSec (optional) and EP
+ firmware */
+#define MGMT_FLASHROM_OPTYPE_CODE_REDBOOT (1)
+#define MGMT_FLASHROM_OPTYPE_CODE_BIOS (2)
+#define MGMT_FLASHROM_OPTYPE_CODE_PXE_BIOS (3)
+#define MGMT_FLASHROM_OPTYPE_CODE_CTRLS (4)
+#define MGMT_FLASHROM_OPTYPE_CFG_IPSEC (5)
+#define MGMT_FLASHROM_OPTYPE_CFG_INI (6)
+#define MGMT_FLASHROM_OPTYPE_ROM_OFFSET_SPECIFIED (7)
+
+/*
+ * --- FLASHROM_TYPE ---
+ * Flash ROM manufacturers supported in the f/w
+ */
+#define INTEL (0)
+#define SPANSION (1)
+#define MICRON (2)
+
+/* --- DDR_CAS_TYPE --- */
+#define CAS_3 (0)
+#define CAS_4 (1)
+#define CAS_5 (2)
+
+/* --- DDR_SIZE_TYPE --- */
+#define SIZE_256MB (0)
+#define SIZE_512MB (1)
+
+/* --- DDR_MODE_TYPE --- */
+#define DDR_NO_ECC (0)
+#define DDR_ECC (1)
+
+/* --- INTERFACE_10GB_TYPE --- */
+#define CX4_TYPE (0)
+#define XFP_TYPE (1)
+
+/* --- BE_CHIP_MAX_MTU --- */
+#define CHIP_MAX_MTU (9000)
+
+/* --- XAUI_STATE_ENUM --- */
+#define XAUI_STATE_ENABLE (0) /* This MUST be the default
+ value for all requests
+ which set/change
+ equalization parameter. */
+#define XAUI_STATE_DISABLE (255) /* The XAUI for both ports
+ may be disabled for EMI
+ tests. There is no
+ provision for turning off
+ individual ports.
+ */
+/* --- BE_ASIC_REVISION --- */
+#define BE_ASIC_REV_A0 (1)
+#define BE_ASIC_REV_A1 (2)
+
+#endif /* __fwcmd_common_amap_h__ */
diff --git a/drivers/net/benet/host_struct.h b/drivers/net/benet/host_struct.h
new file mode 100644
index 0000000..3de6722
--- /dev/null
+++ b/drivers/net/benet/host_struct.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __host_struct_amap_h__
+#define __host_struct_amap_h__
+#include "be_cm.h"
+#include "be_common.h"
+#include "descriptors.h"
+
+/* --- EQ_COMPLETION_MAJOR_CODE_ENUM --- */
+#define EQ_MAJOR_CODE_COMPLETION (0) /* Completion event on a */
+ /* qcompletion ueue. */
+#define EQ_MAJOR_CODE_ETH (1) /* Affiliated Ethernet Event. */
+#define EQ_MAJOR_CODE_RESERVED (2) /* Reserved */
+#define EQ_MAJOR_CODE_RDMA (3) /* Affiliated RDMA Event. */
+#define EQ_MAJOR_CODE_ISCSI (4) /* Affiliated ISCSI Event */
+#define EQ_MAJOR_CODE_UNAFFILIATED (5) /* Unaffiliated Event */
+
+/* --- EQ_COMPLETION_MINOR_CODE_ENUM --- */
+#define EQ_MINOR_CODE_COMPLETION (0) /* Completion event on a */
+ /* completion queue. */
+#define EQ_MINOR_CODE_OTHER (1) /* Other Event (TBD). */
+
+/* Queue Entry Definition for all 4 byte event queue types. */
+struct BE_EQ_ENTRY_AMAP {
+ u8 Valid; /* DWORD 0 */
+ u8 MajorCode[3]; /* DWORD 0 */
+ u8 MinorCode[12]; /* DWORD 0 */
+ u8 ResourceID[16]; /* DWORD 0 */
+} __packed;
+struct EQ_ENTRY_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * --- ETH_EVENT_CODE ---
+ * These codes are returned by the MPU when one of these events has occurred,
+ * and the event is configured to report to an Event Queue when an event
+ * is detected.
+ */
+#define ETH_EQ_LINK_STATUS (0) /* Link status change event */
+ /* detected. */
+#define ETH_EQ_WATERMARK (1) /* watermark event detected. */
+#define ETH_EQ_MAGIC_PKT (2) /* magic pkt event detected. */
+#define ETH_EQ_ACPI_PKT0 (3) /* ACPI interesting packet */
+ /* detected. */
+#define ETH_EQ_ACPI_PKT1 (3) /* ACPI interesting packet */
+ /* detected. */
+#define ETH_EQ_ACPI_PKT2 (3) /* ACPI interesting packet */
+ /* detected. */
+#define ETH_EQ_ACPI_PKT3 (3) /* ACPI interesting packet */
+ /* detected. */
+
+/*
+ * --- ETH_TX_COMPL_STATUS_ENUM ---
+ * Status codes contained in Ethernet TX completion descriptors.
+ */
+#define ETH_COMP_VALID (0)
+#define ETH_COMP_ERROR (1)
+#define ETH_COMP_INVALID (15)
+
+/*
+ * --- ETH_TX_COMPL_PORT_ENUM ---
+ * Port indicator contained in Ethernet TX completion descriptors.
+ */
+#define ETH_COMP_PORT0 (0)
+#define ETH_COMP_PORT1 (1)
+#define ETH_COMP_MGMT (2)
+
+/*
+ * --- ETH_TX_COMPL_CT_ENUM ---
+ * Completion type indicator contained in Ethernet TX completion descriptors.
+ */
+#define ETH_COMP_ETH (0)
+
+/*
+ * Work request block that the driver issues to the chip for
+ * Ethernet transmissions. All control fields must be valid in each WRB for
+ * a message. The controller, as specified by the flags, optionally writes
+ * an entry to the Completion Ring and generate an event.
+ */
+struct BE_ETH_WRB_AMAP {
+ u8 frag_pa_hi[32]; /* DWORD 0 */
+ u8 frag_pa_lo[32]; /* DWORD 1 */
+ u8 complete; /* DWORD 2 */
+ u8 event; /* DWORD 2 */
+ u8 crc; /* DWORD 2 */
+ u8 forward; /* DWORD 2 */
+ u8 ipsec; /* DWORD 2 */
+ u8 mgmt; /* DWORD 2 */
+ u8 ipcs; /* DWORD 2 */
+ u8 udpcs; /* DWORD 2 */
+ u8 tcpcs; /* DWORD 2 */
+ u8 lso; /* DWORD 2 */
+ u8 last; /* DWORD 2 */
+ u8 vlan; /* DWORD 2 */
+ u8 dbg[3]; /* DWORD 2 */
+ u8 hash_val[3]; /* DWORD 2 */
+ u8 lso_mss[14]; /* DWORD 2 */
+ u8 frag_len[16]; /* DWORD 3 */
+ u8 vlan_tag[16]; /* DWORD 3 */
+} __packed;
+struct ETH_WRB_AMAP {
+ u32 dw[4];
+};
+
+/* This is an Ethernet transmit completion descriptor */
+struct BE_ETH_TX_COMPL_AMAP {
+ u8 user_bytes[16]; /* DWORD 0 */
+ u8 nwh_bytes[8]; /* DWORD 0 */
+ u8 lso; /* DWORD 0 */
+ u8 rsvd0[7]; /* DWORD 0 */
+ u8 wrb_index[16]; /* DWORD 1 */
+ u8 ct[2]; /* DWORD 1 */
+ u8 port[2]; /* DWORD 1 */
+ u8 rsvd1[8]; /* DWORD 1 */
+ u8 status[4]; /* DWORD 1 */
+ u8 rsvd2[16]; /* DWORD 2 */
+ u8 ringid[11]; /* DWORD 2 */
+ u8 hash_val[4]; /* DWORD 2 */
+ u8 valid; /* DWORD 2 */
+ u8 rsvd3[32]; /* DWORD 3 */
+} __packed;
+struct ETH_TX_COMPL_AMAP {
+ u32 dw[4];
+};
+
+/* Ethernet Receive Buffer descriptor */
+struct BE_ETH_RX_D_AMAP {
+ u8 fragpa_hi[32]; /* DWORD 0 */
+ u8 fragpa_lo[32]; /* DWORD 1 */
+} __packed;
+struct ETH_RX_D_AMAP {
+ u32 dw[2];
+};
+
+/* This is an Ethernet Receive Completion Descriptor */
+struct BE_ETH_RX_COMPL_AMAP {
+ u8 vlan_tag[16]; /* DWORD 0 */
+ u8 pktsize[14]; /* DWORD 0 */
+ u8 port; /* DWORD 0 */
+ u8 rsvd0; /* DWORD 0 */
+ u8 err; /* DWORD 1 */
+ u8 rsshp; /* DWORD 1 */
+ u8 ipf; /* DWORD 1 */
+ u8 tcpf; /* DWORD 1 */
+ u8 udpf; /* DWORD 1 */
+ u8 ipcksm; /* DWORD 1 */
+ u8 tcpcksm; /* DWORD 1 */
+ u8 udpcksm; /* DWORD 1 */
+ u8 macdst[6]; /* DWORD 1 */
+ u8 vtp; /* DWORD 1 */
+ u8 vtm; /* DWORD 1 */
+ u8 fragndx[10]; /* DWORD 1 */
+ u8 ct[2]; /* DWORD 1 */
+ u8 ipsec; /* DWORD 1 */
+ u8 numfrags[3]; /* DWORD 1 */
+ u8 rsvd1[31]; /* DWORD 2 */
+ u8 valid; /* DWORD 2 */
+ u8 rsshash[32]; /* DWORD 3 */
+} __packed;
+struct ETH_RX_COMPL_AMAP {
+ u32 dw[4];
+};
+
+#endif /* __host_struct_amap_h__ */
diff --git a/drivers/net/benet/post_codes.h b/drivers/net/benet/post_codes.h
new file mode 100644
index 0000000..6d1621f
--- /dev/null
+++ b/drivers/net/benet/post_codes.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __post_codes_amap_h__
+#define __post_codes_amap_h__
+
+/* --- MGMT_HBA_POST_STAGE_ENUM --- */
+#define POST_STAGE_POWER_ON_RESET (0) /* State after a cold or warm boot. */
+#define POST_STAGE_AWAITING_HOST_RDY (1) /* ARM boot code awaiting a
+ go-ahed from the host. */
+#define POST_STAGE_HOST_RDY (2) /* Host has given go-ahed to ARM. */
+#define POST_STAGE_BE_RESET (3) /* Host wants to reset chip, this is a chip
+ workaround */
+#define POST_STAGE_SEEPROM_CS_START (256) /* SEEPROM checksum
+ test start. */
+#define POST_STAGE_SEEPROM_CS_DONE (257) /* SEEPROM checksum test
+ done. */
+#define POST_STAGE_DDR_CONFIG_START (512) /* DDR configuration start. */
+#define POST_STAGE_DDR_CONFIG_DONE (513) /* DDR configuration done. */
+#define POST_STAGE_DDR_CALIBRATE_START (768) /* DDR calibration start. */
+#define POST_STAGE_DDR_CALIBRATE_DONE (769) /* DDR calibration done. */
+#define POST_STAGE_DDR_TEST_START (1024) /* DDR memory test start. */
+#define POST_STAGE_DDR_TEST_DONE (1025) /* DDR memory test done. */
+#define POST_STAGE_REDBOOT_INIT_START (1536) /* Redboot starts execution. */
+#define POST_STAGE_REDBOOT_INIT_DONE (1537) /* Redboot done execution. */
+#define POST_STAGE_FW_IMAGE_LOAD_START (1792) /* Firmware image load to
+ DDR start. */
+#define POST_STAGE_FW_IMAGE_LOAD_DONE (1793) /* Firmware image load
+ to DDR done. */
+#define POST_STAGE_ARMFW_START (2048) /* ARMfw runtime code
+ starts execution. */
+#define POST_STAGE_DHCP_QUERY_START (2304) /* DHCP server query start. */
+#define POST_STAGE_DHCP_QUERY_DONE (2305) /* DHCP server query done. */
+#define POST_STAGE_BOOT_TARGET_DISCOVERY_START (2560) /* Boot Target
+ Discovery Start. */
+#define POST_STAGE_BOOT_TARGET_DISCOVERY_DONE (2561) /* Boot Target
+ Discovery Done. */
+#define POST_STAGE_RC_OPTION_SET (2816) /* Remote configuration
+ option is set in SEEPROM */
+#define POST_STAGE_SWITCH_LINK (2817) /* Wait for link up on switch */
+#define POST_STAGE_SEND_ICDS_MESSAGE (2818) /* Send the ICDS message
+ to switch */
+#define POST_STAGE_PERFROM_TFTP (2819) /* Download xml using TFTP */
+#define POST_STAGE_PARSE_XML (2820) /* Parse XML file */
+#define POST_STAGE_DOWNLOAD_IMAGE (2821) /* Download IMAGE from
+ TFTP server */
+#define POST_STAGE_FLASH_IMAGE (2822) /* Flash the IMAGE */
+#define POST_STAGE_RC_DONE (2823) /* Remote configuration
+ complete */
+#define POST_STAGE_REBOOT_SYSTEM (2824) /* Upgrade IMAGE done,
+ reboot required */
+#define POST_STAGE_MAC_ADDRESS (3072) /* MAC Address Check */
+#define POST_STAGE_ARMFW_READY (49152) /* ARMfw is done with POST
+ and ready. */
+#define POST_STAGE_ARMFW_UE (61440) /* ARMfw has asserted an
+ unrecoverable error. The
+ lower 3 hex digits of the
+ stage code identify the
+ unique error code.
+ */
+
+/* This structure defines the format of the MPU semaphore
+ * register when used for POST.
+ */
+struct BE_MGMT_HBA_POST_STATUS_STRUCT_AMAP {
+ u8 stage[16]; /* DWORD 0 */
+ u8 rsvd0[10]; /* DWORD 0 */
+ u8 iscsi_driver_loaded; /* DWORD 0 */
+ u8 option_rom_installed; /* DWORD 0 */
+ u8 iscsi_ip_conflict; /* DWORD 0 */
+ u8 iscsi_no_ip; /* DWORD 0 */
+ u8 backup_fw; /* DWORD 0 */
+ u8 error; /* DWORD 0 */
+} __packed;
+struct MGMT_HBA_POST_STATUS_STRUCT_AMAP {
+ u32 dw[1];
+};
+
+/* --- MGMT_HBA_POST_DUMMY_BITS_ENUM --- */
+#define POST_BIT_ISCSI_LOADED (26)
+#define POST_BIT_OPTROM_INST (27)
+#define POST_BIT_BAD_IP_ADDR (28)
+#define POST_BIT_NO_IP_ADDR (29)
+#define POST_BIT_BACKUP_FW (30)
+#define POST_BIT_ERROR (31)
+
+/* --- MGMT_HBA_POST_DUMMY_VALUES_ENUM --- */
+#define POST_ISCSI_DRIVER_LOADED (67108864)
+#define POST_OPTROM_INSTALLED (134217728)
+#define POST_ISCSI_IP_ADDRESS_CONFLICT (268435456)
+#define POST_ISCSI_NO_IP_ADDRESS (536870912)
+#define POST_BACKUP_FW_LOADED (1073741824)
+#define POST_FATAL_ERROR (2147483648)
+
+#endif /* __post_codes_amap_h__ */
--
1.5.5
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