Date:	Wed, 10 Dec 2008 10:04:55 +0100
From:	"Miguel Ángel Álvarez" <gotzoncabanes@...il.com>
To:	"Krzysztof Halasa" <khc@...waw.pl>
Cc:	netdev@...r.kernel.org
Subject: Re: qmgr for ixp4xx

Hi

2008/12/10 Krzysztof Halasa <khc@...waw.pl>:
> "Miguel Ángel Álvarez" <gotzoncabanes@...il.com> writes:
>
>> Sure... But in case you are not using ethernet in the NPEA (most
>> likely if you are using HSS),
>
> I'm not sure but it may be true.
> The docs say things about "6 ports" but AFAIK there are 3 physical
> ports. For now I don't have anything 465-bases so I care a bit less
> than for 425.
>
ixp465 has only 3 ethernet ports I think. NPEA, NPEB and NPEC.

>> ethernet only takes one common queue
>> (TXDONE = 31). The rest of the queues seem to be NPE dependent.
>
> Some numbers are fixed in software (like most of the Ethernet's
> excluding "txready" which is a driver-only thing, and as Christian
> writes, a couple of queues for crypto). Some are configurable (like RX
> Ethernet queues, up to 8 per port with (not unused currently) QoS
> "acceleration").
>
Wouldn't it be interesting to have a list of all the fixed queues?
Let me try:
0-10 HSS1 (fixed)
12-22 HSS0 (fixed)
23 TXqueue NPEA (fixed)
24 TXqueue NPEB (fixed)
25 TXqueue NPEC (fixed)
26 RXfreequeue NPEA (fixed)
27 RXfreequeue NPEB (fixed)
28 RXfreequeue NPEC (fixed)
29,30 Criptocode (fixed)
31 Ethernet TXDONE (fixed)

Now supposing that we want to use three ethernets, two HSS and the
Criptocode, we need two additional queues for each ethernet (rxq and
txreadyq), and 2*4 additional queues for txreadyq for the possible 8
HDLC (4 per HSS) channels.

Am I right?

If we add 64 queue patch, we could give a fixed queue for each of this needs.

If not, in my case that I do not use ethernet in NPEA, criptocode and
HSSX_CHL_RXTRIG_QUEUEs, I have the following spare queues: 10, 11, 12,
23, 26, 29 and 30 (true?). Ummm... seven queues for eight txreadyq...
bad!!!

>> At
>> least that was what I thought, but if I change rxq and txreadyq for
>> ethernet in ixdp425-setup.c and give them the values 0x103, 0x114 for
>> NPEB and 0x203, 0x214 for NPEC they also interfere with the queues for
>> HSS (for not 0 hdlcs...).
>
> The range is 0-31 (0-0x1F). There are (not yet supported) queues 32-64
> (0x20-0x3F) with a bit more limited functionality. We certainly need
> them, too.
>
> And the on-chip SRAM region in which the queues exist is limited, too.
>
You are right... I was thinking the queues were different for each NPE
but they are not.

>> So... Do we have 32 queues for NPE, or some of them are common for all
>> NPEs? In the first case it could be possible to work with 32 queues in
>> most of the situations... if not, 64-queue patch seems to be required
>> (where can I find last version of it? I just found one which is
>> heavily critizised by you, Krzysztof).
>
> It's this one. It wasn't "heavily criticized", though. I didn't like
> many tiny bits but generally it is a good work.
>
OK. Sorry for saying "heavily criticized". Just wanted to state that
it seems not good enough for you to be added in your tree.

> We have 64 queues for all ports, processes etc combined.
> You may want to see Intel's docs, for instance their IXP42X
> development manual (the queues are explained in section 21, "AHB Queue
> Manager (AQM)).
>
RTFM... I was so centered in the lack of information of NPEs that I
did not realized that the queue manager had a chapter in the
developer's manual. Sorry. I have read it and things seem a bit
clearer now.

Thanks

Miguel Ángel
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