netdev - Re: [RFC 5/5] [powerpc] Implement a p1010rdb clock source.

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Date:	Mon, 8 Aug 2011 07:48:42 -0500
From:	Robin Holt <holt@....com>
To:	Marc Kleine-Budde <mkl@...gutronix.de>
Cc:	Robin Holt <holt@....com>, Wolfgang Grandegger <wg@...ndegger.com>,
	U Bhaskar-B22300 <B22300@...escale.com>,
	socketcan-core@...ts.berlios.de, netdev@...r.kernel.org
Subject: Re: [RFC 5/5] [powerpc] Implement a p1010rdb clock source.

On Mon, Aug 08, 2011 at 02:07:32PM +0200, Marc Kleine-Budde wrote:
> On 08/08/2011 01:31 PM, Robin Holt wrote:
> > On Mon, Aug 08, 2011 at 10:37:58AM +0200, Wolfgang Grandegger wrote:
> >> On 08/06/2011 04:34 PM, Robin Holt wrote:
> >>> flexcan driver needs the clk_get, clk_get_rate, etc functions
> >>> to work.  This patch provides the minimum functionality.
> >>
> >> This needs some more general thoughts... apart from the question where
> >> the code should go.
> >>
> >> Like for the MSCAN on the MPC5200, the user should be *able* to select
> >> an appropriate clock source and divider via DTS node properties.
> >> Currently it seems, that the DTS properties must match some
> >> pre-configured values, most likely set by the boot loader. Please
> >> correct me if I'm wrong. For me this is generic and should go into the
> >> Flexcan driver. From there, a platform specific function, e.g.
> >> flexcan_set_clock() might be called.
> > 
> > OK.  Dug a bit more.  The p1010 built-in clocksource seems to be the
> > periphereal clock frequency which is system bus frequency divided
> > by 2.  The clock source can not be changed, but the clock divider can
> > by freezing the interface and setting the CTRL register.  This appears
> 
> Which bit(s) in the CTRL register is/are this?

PRESDIV bits 24-31.  Documented on the P1010 reference manual section 21.3.3.2.

Robin
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