netdev - RE: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations

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Date:	Wed, 22 Aug 2012 15:42:08 +0100
From:	"David Laight" <David.Laight@...LAB.COM>
To:	"Linus Torvalds" <torvalds@...ux-foundation.org>,
	"Ben Hutchings" <bhutchings@...arflare.com>
Cc:	"H. Peter Anvin" <hpa@...or.com>,
	"David Miller" <davem@...emloft.net>, <tglx@...utronix.de>,
	<mingo@...hat.com>, <netdev@...r.kernel.org>,
	<linux-net-drivers@...arflare.com>, <x86@...nel.org>
Subject: RE: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations

> Any patch that exports some "atomic 128-bit MMIO writes" for general
> use sounds totally and utterly broken. You can't do it. It's
> *fundamentally* an operation that many CPU's cannot even do. 64-bit
> buses (or even 32-bit ones) will make the 128-bit write be split up
> *anyway*, regardless of any 128-bit register issues.
> 
> And nobody else sane cares about this, so it shouldn't even be a
> x86-64 specific thing...

There are several other processors that can generate long
PCIe transfers, sometimes by using a DMA engine associated
with the PCIe interface (eg freescale 83xx ppc).

Given the slow speed of PCIe transactions (think ISA bus
speeds - at least with some targets), it is important to
be able to request multi-word transfers in a generic way
on systems that can support it.

This support is a property of the PCIe interface block,
not that of the driver that wishes to use the function.

I don't know if XMM register transfers generate 16byte
TLP on any x86 cpus - they might on some.

Perhaps claiming the function is atomic is the real
problem - otherwise a single TLP could be used on
systems (and in contexts) where it is possible, but
a slower mulit-TLP transfer done (possibly without
guaranteeing the transfer order) done where it is not.

	David

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