netdev - RE: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

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Date:	Wed, 13 Mar 2013 15:43:13 -0000
From:	"David Laight" <David.Laight@...LAB.COM>
To:	"Vipul Pandya" <vipul@...lsio.com>,
	"Steve Wise" <swise@...ngridcomputing.com>
Cc:	"David Miller" <davem@...emloft.net>, <netdev@...r.kernel.org>,
	<linux-rdma@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
	<roland@...estorage.com>, <JBottomley@...allels.com>,
	"Dimitrios Michailidis" <dm@...lsio.com>,
	"Casey Leedom" <leedom@...lsio.com>,
	"Naresh Kumar Inna" <naresh@...lsio.com>,
	"Divy Le Ray" <divy@...lsio.com>,
	"Santosh Rastapur" <santosh@...lsio.com>,
	"Arvind Bhushan" <arvindb@...lsio.com>,
	"Abhishek Agrawal" <abhishek@...lsio.com>
Subject: RE: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

> >>> +				writel(n,  adap->bar2 + q->udb + 8);
> >>> +#if defined(CONFIG_X86_32) || defined(CONFIG_X86_64)
> >>> +			asm volatile("sfence" : : : "memory");
> >>> +#endif
> >> There is absolutely no way I'm letting anyone put crap like this
> >> into a driver.
> >>
> >> Use a portable inteface, and if one does not exist create one.
> >
> > I guess you'll have to add a wc_wmb() function for all the hw platforms
> > supported by the kernel.  I see libibverbs defines this for the user
> > side in include/infiniband/arch.h, and that could be used as the meat of
> > the hw platform-specific implementations.
> >
> I see that normal wmb() code for x86_64 architecture is same as what
> above #ifdef condition is doing. To be more clear I looked at the
> assembly code for wmb and find that it is converted into 'sfence'
> instruction. So, I think above code should be replaced with wmb call
> which will also take care of portability on different architecture. I
> will submit the series again soon.

>From my recollection of the x86 architecture, the memory barriers
are hardly ever needed, certainly not in the places where, for example
a ppc needs them. I'd actually suspect that the normal wmb() for
x86 should be a nop.

About the only place where any on the fence instructions are needed
are in relation to write combining accesses.
In particular I don't believe they are ever needed to synchronise
uncached accesses with each other, or with cached accesses (which
are snooped).

	David




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