lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 17 Apr 2013 17:14:04 +0530
From:	Mugunthan V N <mugunthanvnm@...com>
To:	Sebastian Andrzej Siewior <bigeasy@...utronix.de>
CC:	Richard Cochran <richardcochran@...il.com>,
	<netdev@...r.kernel.org>, "David S. Miller" <davem@...emloft.net>,
	Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH] net/cpsw: don't disable_irqs() after an interrupt has
 been received.

On 4/17/2013 4:19 PM, Sebastian Andrzej Siewior wrote:
> On 04/17/2013 12:08 PM, Mugunthan V N wrote:
>> Mine shows [    0.000000] AM335X ES2.0 (neon )
>>
>> In Beagle bone (silicon revision 1.0) there is a bug in CPSW irq in
>> Silicon, please refer
>> http://www.ti.com/lit/er/sprz360e/sprz360e.pdf  Advisory 1.0.9
>>
>> Beagle bone black has Silicon revision 2.0 where the bug is fixed and
>> you are able
>> to test it properly and it hangs in my bone black as the IRQ is properly
>> connected
>> to A8
> Okay. This would explain things. So let me try it again without
> breaking the new one. If you disable_irq() there is no need to mask the
> source in chip, right?
>
Yes, May be we can try. If the performance is more then we can think of 
removing
disabling interrupt in CPSW and use only disable ARM irq.

Regards
Mugunthan V N
--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ