netdev - Re: [net-next PATCH 0/4] cpsw: support for control module register

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Date:	Tue, 24 Sep 2013 10:34:16 -0400 (EDT)
From:	David Miller <davem@...emloft.net>
To:	mugunthanvnm@...com
Cc:	netdev@...r.kernel.org, zonque@...il.com, bcousson@...libre.com,
	tony@...mide.com, devicetree@...r.kernel.org,
	linux-omap@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [net-next PATCH 0/4] cpsw: support for control module register

From: Mugunthan V N <mugunthanvnm@...com>
Date: Sat, 21 Sep 2013 00:50:37 +0530

> This patch series adds the support for configuring GMII_SEL register
> of control module to select the phy mode type and also to configure
> the clock source for RMII phy mode whether to use internal clock or
> the external clock from the phy itself.
> 
> Till now CPSW works as this configuration is done in U-Boot and carried
> over to the kernel. But during suspend/resume Control module tends to
> lose its configured value for GMII_SEL register in AM33xx PG1.0, so
> if CPSW is used in RMII or RGMII mode, on resume cpsw is not working
> as GMII_SEL register lost its configuration values.
> 
> The initial version of the patch is done by Daniel Mack but as per
> Tony's comment he wants it as a seperate driver as it is done in USB
> control module. I have created a seperate driver for the same.

Series applied, thanks.
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