netdev - Re: [PATCH v2] can: xilinx CAN controller support.

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Date:	Fri, 14 Feb 2014 10:16:20 +0100
From:	Marc Kleine-Budde <mkl@...gutronix.de>
To:	monstr@...str.eu
CC:	Kedareswara rao Appana <appana.durga.rao@...inx.com>,
	wg@...ndegger.com, michal.simek@...inx.com,
	grant.likely@...aro.org, robh+dt@...nel.org,
	linux-can@...r.kernel.org, netdev@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	Kedareswara rao Appana <appanad@...inx.com>
Subject: Re: [PATCH v2] can: xilinx CAN controller support.

On 02/14/2014 10:13 AM, Michal Simek wrote:
>>> That's not entirely truth. If you look at Microblaze then you will see
>>> that Microblaze can be BE and LE.
>>> There is just missing endian detection which we will add to the next version.
>>
>> As far as I know the endianess of the kernel is fixed and known during
>> compile time. Correct me if I'm wrong. So there is no need for a runtime
>> detection of the endianess and so no need for {read,write}_reg function
>> pointers.
> 
> Endianess of the kernel is fixed and know during compile time
> but what it is not fixed is endianess of that IP at compile time.
> 
> On fpga you can use bridges, partial reconfiguration, etc where
> the only solution which is run-time endian detection via registers.
> 
> For example: drivers/block/xsysace.c, drivers/spi/spi-xilinx.c, etc

Okay, now I get it. You can make it more complex then it used to be :D

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
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