netdev - Re: [patch net-next RFC 0/4] introduce infrastructure for support of switch chip datapath

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Date:	Wed, 26 Mar 2014 14:17:47 +0100
From:	Jiri Pirko <jiri@...nulli.us>
To:	Jamal Hadi Salim <jhs@...atatu.com>
Cc:	Thomas Graf <tgraf@...g.ch>, Neil Horman <nhorman@...driver.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	netdev <netdev@...r.kernel.org>,
	David Miller <davem@...emloft.net>, andy@...yhouse.net,
	dborkman@...hat.com, ogerlitz@...lanox.com, jesse@...ira.com,
	pshelar@...ira.com, azhou@...ira.com,
	Ben Hutchings <ben@...adent.org.uk>,
	Stephen Hemminger <stephen@...workplumber.org>,
	jeffrey.t.kirsher@...el.com, vyasevic <vyasevic@...hat.com>,
	Cong Wang <xiyou.wangcong@...il.com>,
	John Fastabend <john.r.fastabend@...el.com>,
	Eric Dumazet <edumazet@...gle.com>,
	Scott Feldman <sfeldma@...ulusnetworks.com>,
	Lennert Buytenhek <buytenh@...tstofly.org>
Subject: Re: [patch net-next RFC 0/4] introduce infrastructure for support of
 switch chip datapath

Wed, Mar 26, 2014 at 12:00:53PM CET, jhs@...atatu.com wrote:
>On 03/26/14 03:21, Jiri Pirko wrote:
>
>>
>>Creating bonding of the switch ports does not fit into the picture at
>>all. These port netdevices are just a representation of a port. Not
>>actual netdevice where the data goes through.
>>
>>Please consider the case I gave already to this thread:
>>
>>         switch chip
>>    ------------------------
>>     |  |  |  |  |  |   |               CPU
>>    p1 p2 ...pn px py  MNGMNT       -----------
>>                 |  |   |              pcie
>>                 |  |   |         ---------------
>>                 |  |   |          |  NIC0 NIC1
>>                 |  |   ---pcie-----   |   |
>>                 |  ------someMII-------   |
>>                 ---------someMII-----------
>>
>>         NIC0 and NIC1 are ordinary NICs like 8139too for example with no
>>         notion they are connected to a switch. They as completely
>>         independent on the mngmnt iface.
>>
>> There, actual data is coming through NIC0 and NIC1 which is
>> completely separated
>> from the p1...pn,px.px port representations.
>>
>> And if you understand it this way, it makes perfect sense to have a
>> master device
>> for these port representations.
>>
>
>I think you may be looking at some specific board design which has those
>two NICs; there are typically many variations of such boards and they
>have to be each dealt with slightly differently by whoever is
>porting. Important detail is:

It is just an example, nothing more.



>we  already know how to deal with NICs - remove them from the diagram
>and then the discussion is about the switch chip. I am assuming
>the MNGMT interface is where the control is going to be. i.e

* I just tried to emphasize where the actual network traffic in between
  switch chip and CPU flows. That is important to realize I believe.


>I can send table updates there, control the different port
>charasterstics etc.
>So Neil's option #1 is to have a driver controlling that interface
>(->priv).
>There's probably some DMA engine's for the datapath for one or more
>of the ports this driver exposes...

See *.

>Replace PCIE with DSA, a simulation chip, whatever the gazillion
>crazy interfaces the openwrt guys have to deal with and we have
>ourselves a consistent interface.
>
>
>>Btw note this model fits into existing DSA as well I believe. The actual DSA
>>devices whould act as NIC0, NIC1 and what would be added is the switch
>>representation (couple of more netdevices to represent actual HW ports and
>>their master)
>>
>
>Refer to my comments above.
>
>
>cheers,
>jamal
>
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