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Date:	Mon, 26 Oct 2015 20:16:11 -0400
From:	dan.streetman@...onical.com
To:	Jeff Kirsher <jeffrey.t.kirsher@...el.com>
Cc:	Jesse Brandeburg <jesse.brandeburg@...el.com>,
	Shannon Nelson <shannon.nelson@...el.com>,
	Carolyn Wyborny <carolyn.wyborny@...el.com>,
	Don Skidmore <donald.c.skidmore@...el.com>,
	Matthew Vick <matthew.vick@...el.com>,
	John Ronciak <john.ronciak@...el.com>,
	Mitch Williams <mitch.a.williams@...el.com>,
	intel-wired-lan@...ts.osuosl.org, netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Dan Streetman <dan.streetman@...onical.com>,
	Dan Streetman <ddstreet@...e.org>
Subject: [PATCH] ixgbe: Wait for 1ms, not 1us, after RST

From: Dan Streetman <dan.streetman@...onical.com>

The driver currently waits 1us after issuing a RST, but the spec
requires it to wait 1ms.

Signed-off-by: Dan Streetman <dan.streetman@...onical.com>
Signed-off-by: Dan Streetman <ddstreet@...e.org>
---
 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
index 4e75843..147bc65 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
@@ -113,7 +113,12 @@ mac_reset_top:
 
 	/* Poll for reset bit to self-clear indicating reset is complete */
 	for (i = 0; i < 10; i++) {
-		udelay(1);
+		/* sec 8.2.4.1.1 :
+		 * programmers must wait approximately 1 ms after setting before
+		 * attempting to check if the bit has cleared or to access (read
+		 * or write) any other device register.
+		 */
+		mdelay(1);
 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 		if (!(ctrl & IXGBE_CTRL_RST_MASK))
 			break;
-- 
2.5.0

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