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Date: Mon, 29 Feb 2016 14:06:21 +0000 From: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@...renesas.com> To: Marc Kleine-Budde <mkl@...gutronix.de>, "wg@...ndegger.com" <wg@...ndegger.com>, "horms@...ge.net.au" <horms@...ge.net.au>, "magnus.damm@...il.com" <magnus.damm@...il.com>, "robh+dt@...nel.org" <robh+dt@...nel.org>, "pawel.moll@....com" <pawel.moll@....com>, "mark.rutland@....com" <mark.rutland@....com>, "ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>, "galak@...eaurora.org" <galak@...eaurora.org> CC: "linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "linux-can@...r.kernel.org" <linux-can@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>, Chris Paterson <Chris.Paterson2@...esas.com> Subject: RE: [PATCH 1/2] can: rcar_can: Add r8a7795 support Hi Marc, > On 02/29/2016 11:00 AM, Marc Kleine-Budde wrote: > > I think it's better to fix the algorithm. I'll look into it. > > What about: > > > ./can-calc-bit-timing -c 39999998 rcar_can > > Bit timing parameters for rcar_can with 39.999998 MHz ref clock > > nominal real Bitrt nom real SampP > > Bitrate TQ[ns] PrS PhS1 PhS2 SJW BRP Bitrate Error SampP SampP Error > CiBCR > > 1000000 125 2 3 2 1 5 999999 0.0% 75.0% 75.0% 0.0% > 0x40040100 > > 800000 125 3 4 2 1 5 799999 0.0% 80.0% 80.0% 0.0% > 0x60040100 > > 500000 125 6 7 2 1 5 499999 0.0% 87.5% 87.5% 0.0% > 0xc0040100 > > 250000 250 6 7 2 1 10 249999 0.0% 87.5% 87.5% 0.0% > 0xc0090100 > > 125000 500 6 7 2 1 20 124999 0.0% 87.5% 87.5% 0.0% > 0xc0130100 > > 100000 625 6 7 2 1 25 99999 0.0% 87.5% 87.5% 0.0% > 0xc0180100 > > 50000 1250 6 7 2 1 50 49999 0.0% 87.5% 87.5% 0.0% > 0xc0310100 > > 20000 3125 6 7 2 1 125 19999 0.0% 87.5% 87.5% 0.0% > 0xc07c0100 > > 10000 6250 6 7 2 1 250 9999 0.0% 87.5% 87.5% 0.0% > 0xc0f90100 > I think, it should be correct. Can I have the patch please(can-utils or kernel)? I'll give it a go. Manual e.g. shows, for 1Mbps and 40MHz clock, two settings are possible 10Tq -> BRP 4 20Tq -> BRP 2 Condition is TSEG1 > TSEG2 >= SJW & bitrate = clock freq/(brp * number of Tq) Your e.g. satisfies the condition and hopefully it should be OK. Thanks, Ramesh
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