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Date: Tue, 5 Apr 2016 00:22:33 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Maxime Ripard <maxime.ripard@...e-electrons.com>,
Florian Fainelli <f.fainelli@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>
Cc: LABBE Corentin <clabbe.montjoie@...il.com>, netdev@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Chen-Yu Tsai <wens@...e.org>
Subject: [PATCH RFC 4/5] ARM: dts: sun8i-h3: Add Ethernet controller device node to sun8i-h3.dtsi
From: LABBE Corentin <clabbe.montjoie@...il.com>
The Allwinner H3 SoC has a gigabit Ethernet controller.
Signed-off-by: LABBE Corentin <clabbe.montjoie@...il.com>
[wens@...e.org: drop pinmux; update clocks/resets]
Signed-off-by: Chen-Yu Tsai <wens@...e.org>
---
This is not a stable binding. Do not merge.
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 9a28aeba9bc6..7749af6354bb 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -635,6 +635,18 @@
status = "disabled";
};
+ emac: ethernet@...0000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ reg = <0x01c30000 0x1000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ahb_rst 17>;
+ reset-names = "ahb";
+ clocks = <&bus_gates 17>, <&ephy>;
+ clock-names = "ahb", "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gic: interrupt-controller@...81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
2.7.0
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