netdev - Re: Micrel Phy KSZ8031 clock select setting in dts

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Date:	Sun, 19 Jun 2016 21:29:41 +0200
From:	Oliver Graute <oliver.graute@...il.com>
To:	Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
Cc:	netdev@...r.kernel.org, f.fainelli@...il.com, johan@...nel.org,
	bth@...strup.dk, s.hauer@...gutronix.de
Subject: Re: Micrel Phy KSZ8031 clock select setting in dts

On 17/06/16, Sergei Shtylyov wrote:
> On 06/17/2016 04:04 PM, Oliver Graute wrote:
> 
> >I try to enable a Micrel KSZ8031 in my imx6ul board device tree. But i'am
> >struggeling with the setting for KSZPHY_RMII_REF_CLK_SEL BIT(7). In my
> >revision of this Micrel KSZ8031 Phy the Bit(7) has to be true. The 0x1f
> >register must be 0x8180.
> >
> >How can I configure this register setting into my DTS?
> >
> >I already checked Documentation/devicetree/bindings/net/micrel.txt
> >
> >but i'am not sure if this still up to date. There where some reworks
> >after git commit 86dc1342
> >
> >some other commits related to this Phy clock setting I checked
> >
> >commit 1fadee0c3
> >commit b838b4aced
> >
> >my non working device tree blob for the phy is:
> >
> >&fec1 {
> >	pinctrl-names = "default";
> >	pinctrl-0 = <&pinctrl_enet1>;
> >	phy-mode = "rmii";
> >	rmmi-ref-clk-sel = <1>;
> >	phy-handle = <&ethphy0>;
> >	status = "okay";
> >
> >	mdio {
> >		#address-cells = <1>;
> >		#size-cells = <0>;
> >
> >		ethphy0: ethernet-phy@0 {
> >			compatible = "micrel,ksz8031";
> >			reg = <0>;
> >		};
> >	};
> >};
> >
> >
> >some clue how to configure this phy register setting correctly?
> 
>    Tried specifying "micrel,rmii-reference-clock-select-25-mhz"
> property in the PHY node?
> 

No, I expect my RMII reference clock on 50 MHz. So I thought that
rmii-reference-clock-select-25-mhz isn't the right setting for me here.

If I manually set bit 7 in the 0x1f register to true The Phy only works
until the next ifconfig eth0 up/down cycle. After the Phy Reset Bit 7 is
false again and Phy isn't working anymore.


Best Regards,

Oliver