lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 9 Sep 2016 18:26:19 +0000
From:   Chris Brandt <Chris.Brandt@...esas.com>
To:     Sergei Shtylyov <sergei.shtylyov@...entembedded.com>,
        David Miller <davem@...emloft.net>
CC:     Simon Horman <horms+renesas@...ge.net.au>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Daniel Palmer <daniel@...f.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH v2] net: ethernet: renesas: sh_eth: add POST registers for
 rz

On 9/9/2016, Sergei Shtylyov wrote:
> > sh_eth_private *mdp)  {
> >  	if (sh_eth_is_rz_fast_ether(mdp)) {
> >  		sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
> > +		sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
> > +				 TSU_FWSLC);	/* Enable POST registers */
> >  		return;
> >  	}
> 
>     Wait, don't you also need to write 0s to the POST registers like done
> at the end of this function?

Nope.

The sh_eth_chip_reset() function will write to register ARSTR which will do a HW reset on the block and clear all the registers, including all the POST registers.

static struct sh_eth_cpu_data r7s72100_data = {
	.chip_reset	= sh_eth_chip_reset,


So, before sh_eth_tsu_init() is ever called, the hardware will always be reset.


	/* initialize first or needed device */
	if (!devno || pd->needs_init) {
		if (mdp->cd->chip_reset)
			mdp->cd->chip_reset(ndev);

		if (mdp->cd->tsu) {
			/* TSU init (Init only)*/
			sh_eth_tsu_init(mdp);
		}
	}


Therefore there is no reason to set the POST registers back to 0 because they are already at 0 from the reset.


Chris


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ