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Date: Fri, 25 Nov 2016 12:01:28 +0000 From: Måns Rullgård <mans@...sr.com> To: Sebastian Frias <sf84@...oste.net> Cc: Florian Fainelli <f.fainelli@...il.com>, Martin Blumenstingl <martin.blumenstingl@...glemail.com>, Jerome Brunet <jbrunet@...libre.com>, linux-amlogic@...ts.infradead.org, devicetree@...r.kernel.org, netdev@...r.kernel.org, davem@...emloft.net, khilman@...libre.com, mark.rutland@....com, robh+dt@...nel.org, linux-arm-kernel@...ts.infradead.org, alexandre.torgue@...com, peppe.cavallaro@...com, carlo@...one.org, Andrew Lunn <andrew@...n.ch> Subject: Re: [net-next PATCH v1 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay Sebastian Frias <sf84@...oste.net> writes: > On 24/11/16 19:55, Florian Fainelli wrote: >> Le 24/11/2016 à 09:05, Martin Blumenstingl a écrit : >>> Based on what I found it seems that rgmii-id, rgmii-txid and >>> rgmii-rxid are supposed to be handled by the PHY. >> >> Correct, the meaning of PHY_INTERFACE_MODE should be from the >> perspective of the PHY device: >> >> - PHY_INTERFACE_MODE_RGMII_TXID means that the PHY is responsible for >> adding a delay when the MAC transmits (TX MAC -> PHY (delay) -> wire) >> - PHY_INTERFACE_MODE_RGMII_RXID means that the PHY is responsible for >> adding a delay when the MAC receives (RX MAC <- (delay) PHY) <- wire) >> > > Thanks for the explanation. > Actually I had thought that the delay was to account for board routing > (wires) between the MAC and the PHY. > From your explanation it appears that the delay is to account for board > routing (wires) between the PHY and the RJ45 socket. The delay pertains to the RGMII link between MAC and PHY. The external connection is self-clocking. -- Måns Rullgård
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