[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20161222223013.5ho6hn3tokvn3btz@rob-hp-laptop>
Date: Thu, 22 Dec 2016 16:30:13 -0600
From: Rob Herring <robh@...nel.org>
To: Murali Karicheri <m-karicheri2@...com>
Cc: netdev@...r.kernel.org, linux-omap@...r.kernel.org,
grygorii.strashko@...com, mugunthanvnm@...com,
linux-kernel@...r.kernel.org, arnd@...db.de, davem@...emloft.net,
devicetree@...r.kernel.org, mark.rutland@....com
Subject: Re: [PATCH net-next 02/10] net: netcp: ethss: add support of 10gbe
pcsr link status
On Tue, Dec 20, 2016 at 05:09:45PM -0500, Murali Karicheri wrote:
> From: WingMan Kwok <w-kwok2@...com>
>
> The 10GBASE-R Physical Coding Sublayer (PCS-R) module provides
> functionality of a physical coding sublayer (PCS) on data being
> transferred between a demuxed XGMII and SerDes supporting a 16
> or 32 bit interface. From the driver point of view, whether
> a ethernet link is up or not depends also on the status of the
> block-lock bit of the PCSR. This patch adds the checking of that
> bit in order to determine the link status.
I would think this would be a common thing and the phy driver should
provide the status, rather than trying to give the ethernet driver
direct access to the phy registers. Is the PCSR the serdes phy or
registers in addition to that?
Rob
Powered by blists - more mailing lists