lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 1 Feb 2017 11:12:42 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Saeed Mahameed' <saeedm@...lanox.com>,
        "David S. Miller" <davem@...emloft.net>
CC:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        Daniel Jurgens <danielj@...lanox.com>
Subject: RE: [net-next 2/8] net/mlx5: Configure cache line size for start
 and end padding

From: Saeed Mahameed
> Sent: 31 January 2017 20:59
> From: Daniel Jurgens <danielj@...lanox.com>
> 
> There is a hardware feature that will pad the start or end of a DMA to
> be cache line aligned to avoid RMWs on the last cache line. The default
> cache line size setting for this feature is 64B. This change configures
> the hardware to use 128B alignment on systems with 128B cache lines.

What guarantees that the extra bytes are actually inside the receive skb's
head and tail room?

	David

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux - Powered by OpenVZ