netdev - RE: [net-next 2/8] net/mlx5: Configure cache line size for start and end padding

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Date:   Mon, 6 Feb 2017 13:50:23 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Saeed Mahameed' <saeedm@....mellanox.co.il>,
        Daniel Jurgens <danielj@...lanox.com>
CC:     Saeed Mahameed <saeedm@...lanox.com>,
        "David S. Miller" <davem@...emloft.net>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [net-next 2/8] net/mlx5: Configure cache line size for start
 and end padding

From: Saeed Mahameed 
> Sent: 05 February 2017 11:24
> On Thu, Feb 2, 2017 at 4:47 PM, Daniel Jurgens <danielj@...lanox.com> wrote:
> > On 2/1/2017 5:12 AM, David Laight wrote:
> >> From: Saeed Mahameed
> >>> Sent: 31 January 2017 20:59
> >>> From: Daniel Jurgens <danielj@...lanox.com>
> >>>
> >>> There is a hardware feature that will pad the start or end of a DMA to
> >>> be cache line aligned to avoid RMWs on the last cache line. The default
> >>> cache line size setting for this feature is 64B. This change configures
> >>> the hardware to use 128B alignment on systems with 128B cache lines.
> >> What guarantees that the extra bytes are actually inside the receive skb's
> >> head and tail room?
> >>
> >>       David
> >>
> >>
> > The hardware won't over write the length of the posted buffer.  This feature is already enabled and
> defaults to 64B stride, this patch just configures it properly for 128B cache line sizes.
> >
> Right, and next patch will make sure RX stride is aligned to 128B in
> case 128B cacheline size configured into the HW.

Doesn't that mean these patches are in the wrong order?

> > Thanks for reviewing it.

Don't assume I've done anything other than look for obvious fubars/

	David