netdev - RE: [net 2/2] ixgbe: Limit use of 2K buffers on architectures with 256B or larger cache lines

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Date:   Fri, 3 Mar 2017 12:24:33 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Jeff Kirsher' <jeffrey.t.kirsher@...el.com>,
        "davem@...emloft.net" <davem@...emloft.net>
CC:     Alexander Duyck <alexander.h.duyck@...el.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "nhorman@...hat.com" <nhorman@...hat.com>,
        "sassmann@...hat.com" <sassmann@...hat.com>,
        "jogreene@...hat.com" <jogreene@...hat.com>
Subject: RE: [net 2/2] ixgbe: Limit use of 2K buffers on architectures with
 256B or larger cache lines

From: Jeff Kirsher
> Sent: 03 March 2017 02:25
> From: Alexander Duyck <alexander.h.duyck@...el.com>
> 
> On architectures that have a cache line size larger than 64 Bytes we start
> running into issues where the amount of headroom for the frame starts
> shrinking.
> 
> The size of skb_shared_info on a system with a 64B L1 cache line size is
> 320.  This increases to 384 with a 128B cache line, and 512 with a 256B
> cache line.

Perhaps some of the CACHE_LINE_ALIGNED markers don't actually need
to force alignment with large line sizes?

I realise some things have hard requirements for cache alignment
(eg non-coherent dma), but others are just there to limit the number
of cache lines read and/or dirtied.

	David