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Date: Mon, 5 Jun 2017 16:38:29 +0200 From: Jiri Pirko <jiri@...nulli.us> To: netdev@...r.kernel.org Cc: davem@...emloft.net, jhs@...atatu.com, xiyou.wangcong@...il.com, edumazet@...gle.com, alexander.h.duyck@...el.com, stephen@...workplumber.org, daniel@...earbox.net, mlxsw@...lanox.com Subject: [patch net-next 3/6] mlxsw: pci: Fix size of trap_id field in CQE From: Jiri Pirko <jiri@...lanox.com> The "trap_id" is 9bits long. So far, this was not a problem since we used only traps with ids that fit into 8bits. But the ACL traps that are going to be introduced use the 9th bit. Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation") Signed-off-by: Jiri Pirko <jiri@...lanox.com> Reviewed-by: Yotam Gigi <yotamg@...lanox.com> --- drivers/net/ethernet/mellanox/mlxsw/pci_hw.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h index 0af3338..a644120 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h +++ b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h @@ -155,7 +155,7 @@ MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14); /* pci_cqe_trap_id * Trap ID that captured the packet. */ -MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8); +MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9); /* pci_cqe_crc * Length include CRC. Indicates the length field includes -- 2.9.3
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