netdev - Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group

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Date:   Sat, 14 Oct 2017 17:13:32 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     jacopo mondi <jacopo@...ndi.org>
Cc:     Geert Uytterhoeven <geert@...ux-m68k.org>,
        Chris Brandt <Chris.Brandt@...esas.com>, f.fainelli@...il.com,
        netdev@...r.kernel.org
Subject: Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group

> > So your binding whats to look something like
> >
> >         ether: ethernet@...03000 {
> >                 compatible = "renesas,ether-r7s72100";
> >                 reg = <0xe8203000 0x800>,
> >                       <0xe8204800 0x200>;
> >                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> >                 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
> >                 power-domains = <&cpg_clocks>;
> >                 phy-mode = "mii";
> > 		          phy-handle = <&phy0>;
> >                 #address-cells = <1>;
> >                 #size-cells = <0>;
> >
> >                 mdio: bus-bus {
> >                       #address-cells = <1>;
> >                       #size-cells = <0>;
> >
> >                       phy0: ethernet-phy@1 {
> >                             reg = <1>;
> 
> Why reg = <1> ?
> Shouldn't this be 0, or even better with no reg property at all?

This is the address of the PHY on the MDIO bus. There can be up to 32
devices on the bus. I have no idea what address your PHY is using, so
i just picked a value. 0 can be special, so i avoided it.

	Andrew